公开(公告)号：US20240330145A1

公开(公告)日：2024-10-03

申请号：US18193488

申请日：2023-03-30

Applicant: Xilinx, Inc.

Inventor： Elessar Taggart ,  Ishita Ghosh ,  Rishi Bharadwaj Subramanian

IPC: G06F11/34

CPC classification number: G06F11/348 ,  G06F11/3476

Abstract: An integrated circuit includes a high-speed debug port trace circuit. The high-speed debug trace circuit includes a plurality of input receiver circuits each configured to receive a stream of trace data. The plurality of input receiver circuits receive streams of trace data from a plurality of compute circuits of different compute circuit types. The plurality of compute circuits are within the integrated circuit. The high-speed debug trace circuit includes a stream selector circuit configured to perform multiple stages of arbitration among the plurality of streams of trace data to generate output trace data. The stream selector circuit inserts compute circuit type identifiers within the output trace data. Each compute circuit type identifier specifies a compute circuit type that originated each portion of trace data of the output trace data. The high-speed debug trace circuit includes an output transmitter circuit configured to output the output trace data.

公开(公告)号：US11256520B2

公开(公告)日：2022-02-22

申请号：US16574956

申请日：2019-09-18

Applicant: Xilinx, Inc.

Inventor： David P. Schultz ,  Adrian M. Hernandez ,  David Robinson ,  Elessar Taggart ,  Max Heimer

IPC: G06F11/00 ,  G06F9/445 ,  G06F11/07

Abstract: Tracing status of a programmable device can include, in response to loading a device image for the programmable device, determining, using a processing unit on the programmable device, trace data for the device image, storing, by the processing unit, the trace data for the device image in a memory, and, in response to unloading the device image, recording the unloading of the device image in the trace data in the memory.

公开(公告)号：US20240330144A1

公开(公告)日：2024-10-03

申请号：US18193444

申请日：2023-03-30

Applicant: Xilinx, Inc.

Inventor： Ishita Ghosh ,  Elessar Taggart ,  Rishi Bharadwaj Subramanian ,  Jason Richard Villarreal

IPC: G06F11/34

CPC classification number: G06F11/348 ,  G06F11/3476

Abstract: Offloading trace data from an integrated circuit (IC) can include receiving, by a high-speed debug port (HSDP) trace circuit, streams of trace data from a plurality of compute circuits of different compute circuit types. The compute circuits and the HSDP trace circuit are disposed in a same IC. Compute circuit type identifiers are included within the trace data. The compute circuit type identifiers specify the compute circuit type from which respective ones of the streams of the trace data originate. Debug trace packets (DTPs) are generated from the trace data and transmitted over a high-speed communication link to a trace data storage device (TDSD) external to the IC. Within the TDSD, trace data from the DTPs are stored in a memory of the TDSD.

公开(公告)号：US20210081215A1

公开(公告)日：2021-03-18

申请号：US16574956

申请日：2019-09-18

Applicant: Xilinx, Inc.

Inventor： David P. Schultz ,  Adrian M. Hernandez ,  David Robinson ,  Elessar Taggart ,  Max Heimer

IPC: G06F9/445 ,  G06F11/07

Abstract: Tracing status of a programmable device can include, in response to loading a device image for the programmable device, determining, using a processing unit on the programmable device, trace data for the device image, storing, by the processing unit, the trace data for the device image in a memory, and, in response to unloading the device image, recording the unloading of the device image in the trace data in the memory.