公开(公告)号：US10657060B1

公开(公告)日：2020-05-19

申请号：US16224045

申请日：2018-12-18

Applicant: Xilinx, Inc.

Inventor： David Robinson

IPC: G06F13/00 ,  G06F12/0862 ,  G06F15/78 ,  H03K19/17756

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for performing a partial reconfiguration of a partially reconfigurable programmable logic device. One of the methods includes providing, to an external memory device storing partial reconfiguration data, a first modified buffer offset. Before receiving partial reconfiguration data at the first modified buffer offset from the external memory, a first portion of prefetched data stored in local buffer memory is written to a configuration space of the partially reconfigurable device. When a first portion of data at the first modified buffer offset is received from the external memory device, the first portion of data at the first modified buffer offset is written to the configuration space of the partially reconfigurable device.

公开(公告)号：US10305511B1

公开(公告)日：2019-05-28

申请号：US15990151

申请日：2018-05-25

Applicant: Xilinx, Inc.

Inventor： David P. Schultz ,  Weiguang Lu ,  Priyanka Agrawal ,  Jun Liu ,  Sourabh Goyal ,  David Robinson

IPC: H03M7/46 ,  G06F17/50

Abstract: Decompressing a data set includes inputting data units to a decompression circuit and comparing each input data unit to a run value and to a substitute value. In response to the data unit being not equal to the run value or the substitute value, the decompression circuit outputs the value of the input data unit; in response to the input data unit having the run value and a succeeding data unit having a value N not equal to zero or one, the decompression circuit outputs multiple data units having the run value based on the value N; in response to input data unit having the substitute value, the decompression circuit outputs one data unit having the run value; and in response to one input data unit having the run value and a succeeding data unit equal to zero or one, the decompression circuit outputs one data unit of the substitute value.

公开(公告)号：US11256520B2

公开(公告)日：2022-02-22

申请号：US16574956

申请日：2019-09-18

Applicant: Xilinx, Inc.

Inventor： David P. Schultz ,  Adrian M. Hernandez ,  David Robinson ,  Elessar Taggart ,  Max Heimer

IPC: G06F11/00 ,  G06F9/445 ,  G06F11/07

Abstract: Tracing status of a programmable device can include, in response to loading a device image for the programmable device, determining, using a processing unit on the programmable device, trace data for the device image, storing, by the processing unit, the trace data for the device image in a memory, and, in response to unloading the device image, recording the unloading of the device image in the trace data in the memory.

公开(公告)号：US10541686B1

公开(公告)日：2020-01-21

申请号：US16192053

申请日：2018-11-15

Applicant: Xilinx, Inc.

Inventor： David P. Schultz ,  David Robinson ,  Kusuma Bathala ,  Wenyi Song

IPC: H03K19/177

Abstract: A circuit for routing data in an integrated circuit device is described. The circuit comprises an input/output port; an interface circuit coupled to the input/output port and configured to receive data, the interface circuit comprising a selection circuit enabling the selection of the data and a predetermined value; and a control circuit coupled to control the selection circuit; wherein the control circuit holds the input/output port at the predetermined value during a partial reconfiguration of the integrated circuit device in response to a control signal. A method of configuring a circuit for routing data in an integrated circuit device is also described.

公开(公告)号：US10067642B1

公开(公告)日：2018-09-04

申请号：US14639768

申请日：2015-03-05

Applicant: Xilinx, Inc.

Inventor： David Robinson ,  Sumit Nagpal ,  Prashanth Kumar ,  Shreegopal S. Agrawal

IPC: G06F17/30 ,  G06F3/0482 ,  G06F9/38

Abstract: Core processing and parameterization may include detecting, using a processor, a super parameter within a core, and, responsive to the detecting, automatically creating, using the processor, a data structure within a memory element having a hierarchy and having a parameter of the core. The data structure may be set as a value of the super parameter of the core.

公开(公告)号：US20210081215A1

公开(公告)日：2021-03-18

申请号：US16574956

申请日：2019-09-18

Applicant: Xilinx, Inc.

Inventor： David P. Schultz ,  Adrian M. Hernandez ,  David Robinson ,  Elessar Taggart ,  Max Heimer

IPC: G06F9/445 ,  G06F11/07

Abstract: Tracing status of a programmable device can include, in response to loading a device image for the programmable device, determining, using a processing unit on the programmable device, trace data for the device image, storing, by the processing unit, the trace data for the device image in a memory, and, in response to unloading the device image, recording the unloading of the device image in the trace data in the memory.

公开(公告)号：US09183339B1

公开(公告)日：2015-11-10

申请号：US14538595

申请日：2014-11-11

Applicant: Xilinx, Inc.

Inventor： Nabeel Shirazi ,  David Robinson ,  Amit Kasat ,  Arvind Sundararajan

IPC: G06F17/50

CPC classification number: G06F17/5054 ,  G06F17/505

Abstract: A circuit design is created in a computer memory in response to user input to a computer processor. The circuit design has a static portion. A virtual socket is instantiated in the circuit design in response to user input, and one or more reconfigurable modules are instantiated in the virtual socket in response to user input. The static portion of the circuit design is coupled to the one or more reconfigurable modules, and configuration data are generated from the circuit design. The configuration data include a configuration bitstream corresponding to the static portion of the circuit design and one or more partial configuration bitstreams corresponding to the one or more reconfigurable modules.

Abstract translation: 响应于用户对计算机处理器的输入，在计算机存储器中创建电路设计。 电路设计有静态部分。 响应于用户输入，在电路设计中实例化虚拟插座，并且响应于用户输入在虚拟插座中实例化一个或多个可重新配置的模块。 电路设计的静态部分耦合到一个或多个可重新配置的模块，并且从电路设计产生配置数据。 配置数据包括对应于电路设计的静态部分的配置比特流和对应于一个或多个可重新配置模块的一个或多个部分配置比特流。