公开(公告)号：US10949586B1

公开(公告)日：2021-03-16

申请号：US16918228

申请日：2020-07-01

Applicant: Xilinx, Inc.

Inventor： Jaipal R. Nareddy ,  Suman Kumar Timmireddy ,  Rahul Gupta

IPC: G06F30/327 ,  G06F30/394 ,  G06F115/02

Abstract: Approaches for post-synthesis insertion of debug cores include a programmed processor inputting data that identify signals of a synthesized circuit design to be probed and determining whether or not debug cores and interfaces needed to probe the signals are absent from the circuit design. The programmed processor creates, in response to determining that the debug cores and interfaces are absent, the debug cores and interfaces in the circuit design. The programmed processor couples the debug cores and interfaces to the signals in the circuit design and synthesizes the debug cores and interfaces created in the circuit design to create a modified circuit design. The method includes generating a circuit definition from the modified circuit design by the programmed processor, and implementing a circuit that operates according to the circuit definition.

公开(公告)号：US10713403B1

公开(公告)日：2020-07-14

申请号：US16374494

申请日：2019-04-03

Applicant: Xilinx, Inc.

Inventor： Shreegopal S. Agrawal ,  Jaipal R. Nareddy ,  Suman Kumar Timmireddy ,  Benjamin D. Curry ,  Siddharth Rele ,  Sozon Panou

IPC: G06F30/30 ,  G06F30/20 ,  G06F30/31 ,  G06F30/327 ,  G06F30/323

Abstract: Apparatus and associated methods relate to controlling synthesis of an electronic design by tagging an intellectual property (IP) parameter such that changes to the tagged design parameter do not result in the entire electronic design being re-synthesized. In an illustrative example, a circuit may contain a number of hard blocks, which may be configured using an HDL design tool. Whenever an IP parameter of an HDL design is updated, place and route may go out of date, which may require the entire design to be re-synthesized. By tagging certain IP parameters with at least one tag, changes or alterations to these tagged IP parameters will not cause synthesis to occur (for output products associated with the at least one tag). Avoiding re-synthesis may save significant time for designers by performing re-synthesis only when necessary.