公开(公告)号：US11108644B1

公开(公告)日：2021-08-31

申请号：US16399413

申请日：2019-04-30

Applicant: Xilinx, Inc.

Inventor： Garik Mkrtchyan ,  Satish Sivaswamy ,  Jinny Singh

IPC: H04L12/24 ,  H04L12/721 ,  H04L12/935 ,  H04L12/947 ,  H04L12/933

Abstract: Some examples described herein relate to routing in routing elements (e.g., switches). In an example, a design system includes a processor and a memory, storing instruction code, coupled to the processor. The processor is configured to execute the instruction code to model a communication network among switches interconnected in an array of data processing engines (DPEs), generate routes for an application on the modeled communication network, and translate the routes to a file. Each DPE includes a hardened processor core, a memory module, and one or more of the switches. Each switch includes an input or output port that is capable of being shared by multiple routes. Port(s) of each switch are modeled as respective node(s). Generating the routes includes using an A* algorithm that includes a congestion costing function based on a capacity of respective nodes in the modeled communication network and a cumulative demand for the respective nodes.

公开(公告)号：US10565346B1

公开(公告)日：2020-02-18

申请号：US15640009

申请日：2017-06-30

Applicant: Xilinx, Inc.

Inventor： Vishal Suthar ,  Dinesh D. Gaitonde ,  Amit Gupta ,  Jinny Singh

IPC: G06F17/50

Abstract: Implementing a circuit design can include generating an integer linear programming (ILP) formulation for a routing problem by determining constraints for implementing nets of a circuit design within a programmable network-on-chip (NOC) of an integrated circuit, wherein the constraints include placement constraints and routability constraints for the nets. The nets can be simultaneously placed and routed by executing an ILP solver using a processor to minimize an objective function of the ILP formulation while observing the constraints. The ILP solver maps logical units of the nets to interface circuits of the programmable NOC concurrently with mapping the nets to channels of the programmable NOC.