公开(公告)号：US11108644B1

公开(公告)日：2021-08-31

申请号：US16399413

申请日：2019-04-30

Applicant: Xilinx, Inc.

Inventor： Garik Mkrtchyan ,  Satish Sivaswamy ,  Jinny Singh

IPC: H04L12/24 ,  H04L12/721 ,  H04L12/935 ,  H04L12/947 ,  H04L12/933

Abstract: Some examples described herein relate to routing in routing elements (e.g., switches). In an example, a design system includes a processor and a memory, storing instruction code, coupled to the processor. The processor is configured to execute the instruction code to model a communication network among switches interconnected in an array of data processing engines (DPEs), generate routes for an application on the modeled communication network, and translate the routes to a file. Each DPE includes a hardened processor core, a memory module, and one or more of the switches. Each switch includes an input or output port that is capable of being shared by multiple routes. Port(s) of each switch are modeled as respective node(s). Generating the routes includes using an A* algorithm that includes a congestion costing function based on a capacity of respective nodes in the modeled communication network and a cumulative demand for the respective nodes.

公开(公告)号：US11790139B1

公开(公告)日：2023-10-17

申请号：US17722651

申请日：2022-04-18

Applicant: Xilinx, Inc.

Inventor： Satish Sivaswamy ,  Garik Mkrtchyan

IPC: G06F30/31 ,  G06F30/343

CPC classification number: G06F30/31 ,  G06F30/343

Abstract: A design tool determines features of a circuit design and applies a first model to the features. The first model indicates a predicted value of a metric based on the plurality of features. The design tool applies an explanation model to the features, and the explanation model indicates levels of contributions by the features to the predicted value of the metric, respectively. The design tool selects a feature of the plurality of features based on the respective levels of contributions and looks up a recipe associated with the feature in a database having possible features associated with recipes. The design tool processes the circuit design according to the recipe into implementation data that is suitable for making an integrated circuit (IC).

公开(公告)号：US12019964B1

公开(公告)日：2024-06-25

申请号：US17376892

申请日：2021-07-15

Applicant: Xilinx, Inc.

Inventor： Karthic P ,  Paul Kundarewich ,  Satish Sivaswamy ,  Meghraj Kalase ,  Vishal Tripathi ,  Srinivasan Dasasathyan ,  Mehrdad Eslami Dehkordi ,  Xiaojian Yang ,  Amish Pandya

IPC: G06F30/337 ,  G06F30/392 ,  G06N20/00

CPC classification number: G06F30/337 ,  G06F30/392 ,  G06N20/00

Abstract: Methods and systems for selecting between single-process and multi-process implementation flows involve identifying features of a circuit design by a design tool. A classification model is applied to the features. The classification model indicates whether an implementation flow on the circuit design is likely to have a runtime within a first range of runtimes or a runtime within a second range of runtimes. The implementation flow is executed by the design tool in a single process in response to the classification model indicating the implementation flow on the circuit design is likely to have a runtime within the first range of runtimes. The implementation flow is executed by the design tool in a plurality of processes in response to the classification model indicating the implementation flow on the circuit design is likely to have a runtime within the second range of runtimes.

公开(公告)号：US11875100B1

公开(公告)日：2024-01-16

申请号：US17339232

申请日：2021-06-04

Applicant: XILINX, INC.

Inventor： Satish Sivaswamy ,  Ashot Shakhkyan ,  Nitin Deshmukh ,  Garik Mkrtchyan ,  Guenter Stenz ,  Bhasker Pinninti

IPC: G06F30/3947 ,  G06F9/355 ,  G06F9/50 ,  G06F30/347

CPC classification number: G06F30/3947 ,  G06F9/3555 ,  G06F9/5061 ,  G06F30/347

Abstract: Examples described herein provide a non-transitory computer-readable medium storing instructions, which when executed on one or more processors, cause the one or more processors to perform operations. The operations include generating a plurality of child processes according to a number of a plurality of partitions in an integrated circuit (IC) design for an IC die, each of the plurality of child processes corresponding to and assigned to a respective one of the plurality of partitions. The operations include transmitting each of the plurality of partitions to a respective one of the plurality of child processes for routing, each of the plurality of partitions comprising a placement of components for the IC design. The operations include receiving a plurality of routings from the plurality of child processes. The operations include merging the plurality of routings into a global routing for the IC design by assembling together to form a global routing.

公开(公告)号：US20230334205A1

公开(公告)日：2023-10-19

申请号：US17722651

申请日：2022-04-18

Applicant: Xilinx, Inc.

Inventor： Satish Sivaswamy ,  Garik Mkrtchyan

IPC: G06F30/31 ,  G06F30/343

CPC classification number: G06F30/31 ,  G06F30/343

Abstract: A design tool determines features of a circuit design and applies a first model to the features. The first model indicates a predicted value of a metric based on the plurality of features. The design tool applies an explanation model to the features, and the explanation model indicates levels of contributions by the features to the predicted value of the metric, respectively. The design tool selects a feature of the plurality of features based on the respective levels of contributions and looks up a recipe associated with the feature in a database having possible features associated with recipes. The design tool processes the circuit design according to the recipe into implementation data that is suitable for making an integrated circuit (IC).

公开(公告)号：US11604751B1

公开(公告)日：2023-03-14

申请号：US17316584

申请日：2021-05-10

Applicant: XILINX, INC.

Inventor： Brian Guttag ,  Nitin Deshmukh ,  Sreesan Venkatakrishnan ,  Satish Sivaswamy

IPC: G06F13/40

Abstract: Embodiments herein describe techniques for preventing a stall when transmitting data between a producer and a consumer in the same integrated circuit (IC). A stall can occur when there is a split point and a convergence point between the producer and consumer. To prevent the stall, the embodiments herein adjust the latencies of one of the paths (or both paths) such that a maximum latency of the shorter path is greater than, or equal to, the minimum latency of the longer path. When this condition is met, this means the shortest path has sufficient buffers (e.g., a sufficient number of FIFOs and registers) to queue/store packets along its length so that a packet can travel along the longer path and reach the convergence point before the buffers in the shortest path are completely full (or just become completely full).