公开(公告)号：US20230334205A1

公开(公告)日：2023-10-19

申请号：US17722651

申请日：2022-04-18

Applicant: Xilinx, Inc.

Inventor： Satish Sivaswamy ,  Garik Mkrtchyan

IPC: G06F30/31 ,  G06F30/343

CPC classification number: G06F30/31 ,  G06F30/343

Abstract: A design tool determines features of a circuit design and applies a first model to the features. The first model indicates a predicted value of a metric based on the plurality of features. The design tool applies an explanation model to the features, and the explanation model indicates levels of contributions by the features to the predicted value of the metric, respectively. The design tool selects a feature of the plurality of features based on the respective levels of contributions and looks up a recipe associated with the feature in a database having possible features associated with recipes. The design tool processes the circuit design according to the recipe into implementation data that is suitable for making an integrated circuit (IC).

公开(公告)号：US11790139B1

公开(公告)日：2023-10-17

申请号：US17722651

申请日：2022-04-18

Applicant: Xilinx, Inc.

Inventor： Satish Sivaswamy ,  Garik Mkrtchyan

IPC: G06F30/31 ,  G06F30/343

CPC classification number: G06F30/31 ,  G06F30/343

Abstract: A design tool determines features of a circuit design and applies a first model to the features. The first model indicates a predicted value of a metric based on the plurality of features. The design tool applies an explanation model to the features, and the explanation model indicates levels of contributions by the features to the predicted value of the metric, respectively. The design tool selects a feature of the plurality of features based on the respective levels of contributions and looks up a recipe associated with the feature in a database having possible features associated with recipes. The design tool processes the circuit design according to the recipe into implementation data that is suitable for making an integrated circuit (IC).

公开(公告)号：US11875100B1

公开(公告)日：2024-01-16

申请号：US17339232

申请日：2021-06-04

Applicant: XILINX, INC.

Inventor： Satish Sivaswamy ,  Ashot Shakhkyan ,  Nitin Deshmukh ,  Garik Mkrtchyan ,  Guenter Stenz ,  Bhasker Pinninti

IPC: G06F30/3947 ,  G06F9/355 ,  G06F9/50 ,  G06F30/347

CPC classification number: G06F30/3947 ,  G06F9/3555 ,  G06F9/5061 ,  G06F30/347

Abstract: Examples described herein provide a non-transitory computer-readable medium storing instructions, which when executed on one or more processors, cause the one or more processors to perform operations. The operations include generating a plurality of child processes according to a number of a plurality of partitions in an integrated circuit (IC) design for an IC die, each of the plurality of child processes corresponding to and assigned to a respective one of the plurality of partitions. The operations include transmitting each of the plurality of partitions to a respective one of the plurality of child processes for routing, each of the plurality of partitions comprising a placement of components for the IC design. The operations include receiving a plurality of routings from the plurality of child processes. The operations include merging the plurality of routings into a global routing for the IC design by assembling together to form a global routing.

公开(公告)号：US11238206B1

公开(公告)日：2022-02-01

申请号：US17213474

申请日：2021-03-26

Applicant: Xilinx, Inc.

Inventor： Satish B. Sivaswamy ,  Nitin Deshmukh ,  Garik Mkrtchyan ,  Grigor S. Gasparyan

IPC: G06F30/392 ,  G06F30/3312 ,  G06F30/327 ,  G06F30/373 ,  G06F30/3953 ,  G06F30/3947 ,  G06F30/398

Abstract: Performing partition wire assignment for routing a multi-partition circuit design can include performing, using computer hardware, a global assignment phase by clustering a plurality of super-long lines (SLLs) into a plurality of SLL bins, clustering loads of nets of a circuit design into a plurality of load clusters, and assigning the plurality of SLL bins to the plurality of load clusters. For each SLL bin, a detailed assignment phase can be performed wherein each net having a load cluster assigned to the SLL bin is assigned one or more particular SLLs of the SLL bin using the computer hardware.

公开(公告)号：US11709521B1

公开(公告)日：2023-07-25

申请号：US16913716

申请日：2020-06-26

Applicant: Xilinx, Inc.

Inventor： Frederic Revenu ,  Frank Mueller ,  Thomas O. Satter ,  Mehrdad Eslami Dehkordi ,  Garik Mkrtchyan ,  Satish B. Sivaswamy ,  Nicholas A. Mezei ,  Chun Zhang

IPC: G06F1/06

CPC classification number: G06F1/06

Abstract: Synthetizing a hardware description language code into a netlist comprising loads and a multi-clock buffer (MBUF). The MBUF receives a global clocking signal and generates a first and a second related clocking signals. The loads are grouped into a first and a second groups receiving the first and the second clocking signals respectively. A first/second clock modifying leaf are placed between a common node and the first/group groups respectively, wherein the common node is positioned closer in proximity to the first/second groups in comparison to a clock source generating the global clocking signal. The first/second clock modifying leaves receive a least divided clocking signal from the MBUF and generate the first/second clocking signals respectively. The least divided clocking signal is routed from the MBUF to the first/second clock modifying leaves. The first/second clocking signals are routed from the first/second clock modifying leaves to the first/second group respectively.

公开(公告)号：US11108644B1

公开(公告)日：2021-08-31

申请号：US16399413

申请日：2019-04-30

Applicant: Xilinx, Inc.

Inventor： Garik Mkrtchyan ,  Satish Sivaswamy ,  Jinny Singh

IPC: H04L12/24 ,  H04L12/721 ,  H04L12/935 ,  H04L12/947 ,  H04L12/933

Abstract: Some examples described herein relate to routing in routing elements (e.g., switches). In an example, a design system includes a processor and a memory, storing instruction code, coupled to the processor. The processor is configured to execute the instruction code to model a communication network among switches interconnected in an array of data processing engines (DPEs), generate routes for an application on the modeled communication network, and translate the routes to a file. Each DPE includes a hardened processor core, a memory module, and one or more of the switches. Each switch includes an input or output port that is capable of being shared by multiple routes. Port(s) of each switch are modeled as respective node(s). Generating the routes includes using an A* algorithm that includes a congestion costing function based on a capacity of respective nodes in the modeled communication network and a cumulative demand for the respective nodes.

公开(公告)号：US08959474B1

公开(公告)日：2015-02-17

申请号：US14243813

申请日：2014-04-02

Applicant: Xilinx, Inc.

Inventor： Grigor S. Gasparyan ,  Garik Mkrtchyan

IPC: G06F17/50

CPC classification number: G06F17/5077

Abstract: Routing a multi-fanout net includes selecting a driver component of the multi-fanout net of a circuit design, wherein the circuit design is specified programmatically, and determining a plurality of targets of the driver component. A source wave is created at each of a plurality of nodes of the driver component. One target is assigned to each source wave. Each source wave is expanded.

Abstract translation: 路由多扇出网包括选择电路设计的多扇出网络的驱动器组件，其中电路设计以编程方式指定，并且确定驱动器组件的多个目标。 在驱动器部件的多个节点中的每一个处产生源波。 一个目标被分配给每个源波。 每个源波都被扩展。