公开(公告)号：US20230289500A1

公开(公告)日：2023-09-14

申请号：US17692602

申请日：2022-03-11

Applicant: Xilinx, Inc.

Inventor： Anindita Patra ,  Ali Behboodian ,  Michael Gill

IPC: G06F30/31

CPC classification number: G06F30/31

Abstract: Automatically generating a hardware image based on programming model types includes determining by a design tool, types of programming models used in specifications of blocks of a circuit design, in response to a user control input to generate a hardware image to configure a programmable integrated circuit (IC). The design tool can generate a model-type compiler script for each of the types of programming models. Each compiler script initiates compilation of blocks having specifications based on one of the types of programming model into an accelerator representation. The design tool can generate a build script configured to execute the compiler scripts and link the accelerator representations into linked accelerator representations. Execution of the build script builds a hardware image from the linked accelerator representations for configuring the programmable IC to implement a circuit according to the circuit design.

公开(公告)号：US10977018B1

公开(公告)日：2021-04-13

申请号：US16704890

申请日：2019-12-05

Applicant: Xilinx, Inc.

Inventor： L. James Hwang ,  Michael Gill ,  Tom Shui ,  Jorge E. Carrillo ,  Alfred Huang ,  Sudipto Chakraborty

IPC: G06F9/44 ,  G06F8/41 ,  G06F8/30

Abstract: Implementing an application within a heterogeneous device can include receiving an application specifying a plurality of hardware accelerators and having a plurality of sections corresponding to different subsystems of the heterogeneous device, wherein the plurality of sections are specified using different programming models. Compiling each section based on the programming model of the section and the subsystem of the heterogeneous device corresponding to the section into an accelerator representation. Linking the accelerator representations based on a platform of the heterogeneous device, generating a hardware implementation of the application for the heterogeneous device based on the linked accelerator implementations, and automatically generating program code configured to control one or more of the plurality of hardware accelerators of the hardware implementation.

公开(公告)号：US12073155B2

公开(公告)日：2024-08-27

申请号：US17692602

申请日：2022-03-11

Applicant: Xilinx, Inc.

Inventor： Anindita Patra ,  Ali Behboodian ,  Michael Gill

IPC: G06F30/31 ,  G06F30/34

CPC classification number: G06F30/31 ,  G06F30/34

Abstract: Automatically generating a hardware image based on programming model types includes determining by a design tool, types of programming models used in specifications of blocks of a circuit design, in response to a user control input to generate a hardware image to configure a programmable integrated circuit (IC). The design tool can generate a model-type compiler script for each of the types of programming models. Each compiler script initiates compilation of blocks having specifications based on one of the types of programming model into an accelerator representation. The design tool can generate a build script configured to execute the compiler scripts and link the accelerator representations into linked accelerator representations. Execution of the build script builds a hardware image from the linked accelerator representations for configuring the programmable IC to implement a circuit according to the circuit design.

公开(公告)号：US10762265B1

公开(公告)日：2020-09-01

申请号：US16189939

申请日：2018-11-13

Applicant: Xilinx, Inc.

Inventor： Zhenman Fang ,  James L. Hwang ,  Alfred Huang ,  Michael Gill ,  Tom Shui

IPC: G06F30/34 ,  G06F8/38 ,  G06F9/455 ,  G06F9/54 ,  G06F30/327

Abstract: Using a high-level language (HLL) callable library for multiple instances of a core includes detecting, using computer hardware, a reference to an HLL library for a core within an HLL application, determining, using the computer hardware, a plurality of instances of the core by detecting function calls within the HLL application correlated to each of the plurality of instances of the core, and generating, using the computer hardware, interface code within the HLL application for each of the plurality of instances of the core using the HLL library. An executable version of the HLL application is generated, using the computer hardware, wherein the interface code for each of the plurality of instances of the core is bound to the respective instance of the core. The function calls can specify different parameterization files corresponding to the plurality of instances of the core.

公开(公告)号：US10755013B1

公开(公告)日：2020-08-25

申请号：US16189919

申请日：2018-11-13

Applicant: Xilinx, Inc.

Inventor： Zhenman Fang ,  James L. Hwang ,  Samuel A. Skalicky ,  Tom Shui ,  Michael Gill ,  Welson Sun ,  Alfred Huang ,  Jorge E. Carrillo ,  Chen Pan

IPC: G06F30/34 ,  G06F8/41 ,  G06F30/327

Abstract: Creating a high-level language (HLL) callable library for a hardware core can include automatically querying, using computer hardware, a metadata description of a core to determine a plurality of available ports of the core, automatically determining, using the computer hardware, an argument of a first function specified in a header file corresponding to the core, mapping, using the computer hardware, the argument to a first port of the plurality of available ports, and automatically generating and storing, using the computer hardware, an HLL library specifying a mapping of the argument to the first port of the core. The HLL library is configured for inclusion with a user application during compilation.