公开(公告)号：US09824173B1

公开(公告)日：2017-11-21

申请号：US14852173

申请日：2015-09-11

Applicant: Xilinx, Inc.

Inventor： Bennet An ,  Henry E. Styles ,  Sonal Santan ,  Fernando J. Martinez Vallina ,  Pradip K. Jha ,  David A. Knol ,  Sudipto Chakraborty ,  Jeffrey M. Fifield ,  Stephen P. Rozum

IPC: G06F17/50

CPC classification number: G06F17/5054

Abstract: A software development-based compilation flow for circuit design may include executing, using a processor, a makefile including a plurality of rules for hardware implementation. Responsive to executing a first rule of the plurality of rules, a source file including a kernel specified in a high level programming language may be selected; and, an intermediate file specifying a register transfer level implementation of the kernel may be generated using the processor. Responsive to executing a second rule of the plurality of rules, a configuration bitstream for a target integrated circuit may be generated from the intermediate file using the processor. The configuration bitstream includes a compute unit circuit implementation of the kernel.

公开(公告)号：US08839166B1

公开(公告)日：2014-09-16

申请号：US13837234

申请日：2013-03-15

Applicant: Xilinx, Inc.

Inventor： Sudipto Chakraborty ,  David A. Knol ,  Stephen P. Rozum ,  Ryan A. Linderman ,  Derrick S. Woods

IPC: G06F17/50

CPC classification number: G06F17/5054 ,  G06F17/505 ,  G06F2217/66

Abstract: A method, non-transitory computer readable medium and apparatus for using an out-of-context sub-block in a hierarchical design flow for an integrated circuit are disclosed. For example, the method identifies one or more sub-blocks in the hierarchical design flow that are eligible for creating the out-of-context sub-block, receives a selection of one of the one or more sub-blocks that are eligible and creates the out-of-context sub-block for the one of the one or more sub-blocks that is selected.

Abstract translation: 公开了一种用于在集成电路的分层设计流程中使用失去上下文子块的方法，非暂时计算机可读介质和装置。 例如，该方法识别分层设计流程中的一个或多个子块，该子块有资格创建失去上下文的子块，接收一个或多个符合条件并创建的子块中的一个的选择 用于所选择的一个或多个子块中的一个的上下文子块。

公开(公告)号：US20230055704A1

公开(公告)日：2023-02-23

申请号：US17408218

申请日：2021-08-20

Applicant: Xilinx, Inc.

Inventor： Sebastian Turullols ,  Kyle Corbett ,  Sudipto Chakraborty ,  Siva Santosh Kumar Pyla ,  Ravinder Sharma ,  Kaustuv Manji ,  Jayaram PVSS ,  Stephen P. Rozum ,  Ch Vamshi Krishna ,  Susheel Puthana

IPC: G06F30/392 ,  G06F30/3953 ,  G06F30/398

Abstract: Using a flat shell for an accelerator card includes reading a flat shell from one or more computer readable storage media using computer hardware, wherein the flat shell is a synthesized, unplaced, and unrouted top-level circuit design specifying platform circuitry. A kernel specifying user circuitry is synthesized using the computer hardware. The kernel is obtained from the one or more computer readable storage media. The synthesized kernel is linked, using the computer hardware, to the flat shell forming a unified circuit design. The unified circuit design is placed and routed, using the computer hardware, to generate a placed and routed circuit design specifying the platform circuitry and the user circuitry for implementation in an integrated circuit.

公开(公告)号：US10977018B1

公开(公告)日：2021-04-13

申请号：US16704890

申请日：2019-12-05

Applicant: Xilinx, Inc.

Inventor： L. James Hwang ,  Michael Gill ,  Tom Shui ,  Jorge E. Carrillo ,  Alfred Huang ,  Sudipto Chakraborty

IPC: G06F9/44 ,  G06F8/41 ,  G06F8/30

Abstract: Implementing an application within a heterogeneous device can include receiving an application specifying a plurality of hardware accelerators and having a plurality of sections corresponding to different subsystems of the heterogeneous device, wherein the plurality of sections are specified using different programming models. Compiling each section based on the programming model of the section and the subsystem of the heterogeneous device corresponding to the section into an accelerator representation. Linking the accelerator representations based on a platform of the heterogeneous device, generating a hardware implementation of the application for the heterogeneous device based on the linked accelerator implementations, and automatically generating program code configured to control one or more of the plurality of hardware accelerators of the hardware implementation.

公开(公告)号：US10216217B1

公开(公告)日：2019-02-26

申请号：US15382390

申请日：2016-12-16

Applicant: Xilinx, Inc.

Inventor： Sonal Santan ,  Sudipto Chakraborty ,  Fei Rui ,  Stephen P. Rozum ,  Yenpang Lin ,  Yau-Tsun S. Li ,  Sumit Roy

IPC: G06F1/00 ,  G06F1/08

Abstract: Hardware acceleration for a kernel can include selecting, using a processor, a kernel, determining, using the processor, a clock frequency for the selected kernel, and programming, using the processor, a clock circuit to generate a clock signal having a clock frequency compatible with the clock frequency of the selected kernel. Using the processor, the selected kernel can be implemented as a kernel circuit within a region of programmable circuitry. The kernel circuit can be clocked using the clock signal from the clock circuit having the compatible clock frequency.

公开(公告)号：US09864828B1

公开(公告)日：2018-01-09

申请号：US14857634

申请日：2015-09-17

Applicant: Xilinx, Inc.

Inventor： Susheel Kumar Puthana ,  Stephen P. Rozum ,  Sudipto Chakraborty ,  David A. Knol ,  Yong Li ,  Fernando J. Martinez Vallina ,  Sonal Santan ,  Nabeel Shirazi ,  Salil R. Raje ,  Ethan T. Parker ,  Suman Kumar Timmireddy ,  Heera Nand

IPC: G06F17/50

CPC classification number: G06F17/5077 ,  G06F17/5072

Abstract: Implementing hardware accelerators using programmable integrated circuits may include performing, using a processor, a design flow on a static circuit design. The static circuit design may specify a region reserved for a hardware accelerator and a static region comprising interface circuitry configured to couple the hardware accelerator with an external node. The design flow may generate an implemented static circuit design. Metadata describing the interface circuitry may be generated using a processor. A device support archive including the implemented static circuit design and the metadata may be written, using the processor, to a computer readable storage medium.

公开(公告)号：US11720735B2

公开(公告)日：2023-08-08

申请号：US17408218

申请日：2021-08-20

Applicant: Xilinx, Inc.

Inventor： Sebastian Turullols ,  Kyle Corbett ,  Sudipto Chakraborty ,  Siva Santosh Kumar Pyla ,  Ravinder Sharma ,  Kaustuv Manji ,  Jayaram Pvss ,  Stephen P. Rozum ,  Ch Vamshi Krishna ,  Susheel Puthana

IPC: G06F30/392 ,  G06F30/398 ,  G06F30/3953

CPC classification number: G06F30/392 ,  G06F30/398 ,  G06F30/3953

Abstract: Using a flat shell for an accelerator card includes reading a flat shell from one or more computer readable storage media using computer hardware, wherein the flat shell is a synthesized, unplaced, and unrouted top-level circuit design specifying platform circuitry. A kernel specifying user circuitry is synthesized using the computer hardware. The kernel is obtained from the one or more computer readable storage media. The synthesized kernel is linked, using the computer hardware, to the flat shell forming a unified circuit design. The unified circuit design is placed and routed, using the computer hardware, to generate a placed and routed circuit design specifying the platform circuitry and the user circuitry for implementation in an integrated circuit.

公开(公告)号：US09824170B1

公开(公告)日：2017-11-21

申请号：US14989676

申请日：2016-01-06

Applicant: Xilinx, Inc.

Inventor： Alec J. Wong ,  Pradip K. Jha ,  Steven Banks ,  Sudipto Chakraborty ,  Dennis McCrohan

IPC: G06F17/00 ,  G06F17/50

CPC classification number: G06F17/5045 ,  G06F17/5068

Abstract: Message filtering may include, during a first processing phase of a design specified in source code, creating a filter table including message filters and storing the filter table in a memory using a processor. Each message filter may specify a message criterion and an object identifier of the design. During a subsequent processing phase of the design, received messages may be compared with the message filters of the filter table using the processor. Responsive to determining that a selected message matches a message criterion and an object identifier of a selected message filter, the message may be suppressed using the processor.

公开(公告)号：US09679092B1

公开(公告)日：2017-06-13

申请号：US14931650

申请日：2015-11-03

Applicant: Xilinx, Inc.

Inventor： Pradip K. Jha ,  Ravi N. Kurlagunda ,  David A. Knol ,  Dinesh K. Monga ,  Stephen P. Rozum ,  Sudipto Chakraborty

IPC: G06F17/50

CPC classification number: G06F17/5045 ,  G06F17/5022 ,  G06F17/5031 ,  G06F17/504 ,  G06F17/505 ,  G06F2217/84

Abstract: Constraint handling for a circuit design may include determining, using a processor, instances of parameterizable modules of a circuit design associated with constraints based upon a predefined hardware description language attribute within the instances, extracting, using the processor, parameter values from the instances of the parameterizable modules, and generating, using the processor, static constraint files for the instances of the parameterizable modules using the extracted parameter values.

公开(公告)号：US09646118B1

公开(公告)日：2017-05-09

申请号：US14493154

申请日：2014-09-22

Applicant: Xilinx, Inc.

Inventor： Rajvinder S. Klair ,  David A. Knol ,  Sudipto Chakraborty

IPC: G06F17/50

CPC classification number: G06F17/5009 ,  G06F17/5045 ,  G06F2217/04

Abstract: Simulators are linked to a circuit design tool by establishing a plurality of simulator objects in response to a plurality of registration commands, respectively. Each registration command specifies a simulation interface application associated with one of the simulators, and the simulation interface application has procedures for initiating functions of the associated simulator. For each simulator, values of properties of the simulator are stored in the respective simulator object. The values of the properties include references to the procedures of the associated simulation interface application. An interface, which is responsive to input commands, accesses the values of the properties and executes the procedures referenced by the values of the properties to initiate the functions of the simulators.