公开(公告)号：US10242150B1

公开(公告)日：2019-03-26

申请号：US15175897

申请日：2016-06-07

Applicant: Xilinx, Inc.

Inventor： Sabyasachi Das ,  Xiaojian Yang ,  Niyati Shah ,  Govinda Keshavdas ,  Frederic Revenu

IPC: G06F17/50

Abstract: Circuit design implementation can include selecting a first and second load each having a control pin of a same type driven by a different driver, determining whether the driver of the first load matches the driver of the second load, and modifying the circuit design to drive the control pins of the first load and the second load using the driver of the first load. Circuit design implementation can include selecting a net having a driver and a plurality of loads exceeding a threshold, determining a selected module of the circuit design having a number of the plurality of loads of the net that meet a cloning criteria, and, in response, modifying the circuit design by creating a clone of the driver within the selected module and driving each load of the net within the selected module with the clone of the driver.

公开(公告)号：US10303648B1

公开(公告)日：2019-05-28

申请号：US15600534

申请日：2017-05-19

Applicant: Xilinx, Inc.

Inventor： Sabyasachi Das ,  Zhiyong Wang ,  Niyati Shah

IPC: G06F17/50 ,  G06F17/00 ,  G06F15/00 ,  G06F9/30 ,  G06F15/78 ,  G06F9/38 ,  G06F15/80 ,  G06F15/76

Abstract: Implementing a partial reconfiguration design flow can include determining an interface net connecting static circuitry and a first reconfigurable module of a circuit design, performing, using a processor, a logical optimization on first circuitry of the static circuitry that is entirely external to the first reconfigurable module and on second circuitry entirely within the reconfigurable module, and excluding the interface net from processing using the logical optimization.

公开(公告)号：US09965581B1

公开(公告)日：2018-05-08

申请号：US14804134

申请日：2015-07-20

Applicant: Xilinx, Inc.

Inventor： Sabyasachi Das ,  Aaron Ng ,  Ruibing Lu ,  Niyati Shah ,  Zhiyong Wang

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/505 ,  G06F17/5077

Abstract: A method of circuit design may include synthesizing a circuit design using a processor and, for the synthesized circuit design, selectively reducing, using the processor, fanout of nets having a number of loads exceeding a first threshold number of loads and having a selected netlist connectivity. The method may include placing the circuit design using a processor and, for the placed circuit design, selectively reducing, using the processor, fanout of nets according to at least one of a number of loads or criticality.