公开(公告)号：US20230185451A1

公开(公告)日：2023-06-15

申请号：US17643999

申请日：2021-12-13

Applicant: Xilinx, Inc.

Inventor： Vamsi Krishna Nalluri ,  Sai Lalith Chaitanya Ambatipudi ,  Mrinal J. Sarmah ,  Rajeev Patwari ,  Shreyas Manjunath ,  Sandeep Jayant Sathe

IPC: G06F3/06

CPC classification number: G06F3/0608 ,  G06F3/064 ,  G06F3/0673

Abstract: Approaches for data compression involve a compression circuit packing non-zero data elements of a succession of words of a plurality of blocks into packed words by packing non-zero data elements of one or more words of the succession in each packed word, and restricting each packed word to data elements of one uncompressed block. The compression circuit writes each packed word in a RAM and within a compressed address range associated with the uncompressed block when the packed word is full of non-zero data elements, or before the packed word is full if the next input word is of another uncompressed block.

公开(公告)号：US11842168B2

公开(公告)日：2023-12-12

申请号：US17485382

申请日：2021-09-25

Applicant: Xilinx, Inc.

Inventor： Sai Lalith Chaitanya Ambatipudi ,  Vamsi Krishna Nalluri ,  Sandeep Jayant Sathe ,  Chaithanya Dudha ,  Krishna Kishore Bhagavatula

IPC: G06F7/50 ,  G06F7/02 ,  G06F17/18

CPC classification number: G06F7/50 ,  G06F7/026 ,  G06F17/18

Abstract: An electronic system includes a mapping circuit configured to receive input samples of a dataset within a defined range of values. The mapping circuit is configured to perform comparisons that compare each input sample to each of a plurality of comparison values selected from the defined range of values. For each comparison, the mapping circuit generates an indication value specifying whether the input sample used in the comparison is greater than or equal to the comparison value used in the comparison. The system includes an adder circuit configured to generate a sum of the indication values for each comparison value and a memory configured to maintain counts corresponding to the comparison values. The counts are updated by the respective sums. The system includes a threshold detection circuit configured to determine, for the dataset, a threshold value or threshold range based on the counts read from the memory.

公开(公告)号：US11941248B2

公开(公告)日：2024-03-26

申请号：US17643999

申请日：2021-12-13

Applicant: Xilinx, Inc.

Inventor： Vamsi Krishna Nalluri ,  Sai Lalith Chaitanya Ambatipudi ,  Mrinal J. Sarmah ,  Rajeev Patwari ,  Shreyas Manjunath ,  Sandeep Jayant Sathe

IPC: G06F3/06

CPC classification number: G06F3/0608 ,  G06F3/064 ,  G06F3/0673

Abstract: Approaches for data compression involve a compression circuit packing non-zero data elements of a succession of words of a plurality of blocks into packed words by packing non-zero data elements of one or more words of the succession in each packed word, and restricting each packed word to data elements of one uncompressed block. The compression circuit writes each packed word in a RAM and within a compressed address range associated with the uncompressed block when the packed word is full of non-zero data elements, or before the packed word is full if the next input word is of another uncompressed block.

公开(公告)号：US20230096400A1

公开(公告)日：2023-03-30

申请号：US17485382

申请日：2021-09-25

Applicant: Xilinx, Inc.

Inventor： Sai Lalith Chaitanya Ambatipudi ,  Vamsi Krishna Nalluri ,  Sandeep Jayant Sathe ,  Chaithanya Dudha ,  Krishna Kishore Bhagavatula

IPC: G06F7/50

Abstract: An electronic system includes a mapping circuit configured to receive input samples of a dataset within a defined range of values. The mapping circuit is configured to perform comparisons that compare each input sample to each of a plurality of comparison values selected from the defined range of values. For each comparison, the mapping circuit generates an indication value specifying whether the input sample used in the comparison is greater than or equal to the comparison value used in the comparison. The system includes an adder circuit configured to generate a sum of the indication values for each comparison value and a memory configured to maintain counts corresponding to the comparison values. The counts are updated by the respective sums. The system includes a threshold detection circuit configured to determine, for the dataset, a threshold value or threshold range based on the counts read from the memory.