公开(公告)号：US11941248B2

公开(公告)日：2024-03-26

申请号：US17643999

申请日：2021-12-13

Applicant: Xilinx, Inc.

Inventor： Vamsi Krishna Nalluri ,  Sai Lalith Chaitanya Ambatipudi ,  Mrinal J. Sarmah ,  Rajeev Patwari ,  Shreyas Manjunath ,  Sandeep Jayant Sathe

IPC: G06F3/06

CPC classification number: G06F3/0608 ,  G06F3/064 ,  G06F3/0673

Abstract: Approaches for data compression involve a compression circuit packing non-zero data elements of a succession of words of a plurality of blocks into packed words by packing non-zero data elements of one or more words of the succession in each packed word, and restricting each packed word to data elements of one uncompressed block. The compression circuit writes each packed word in a RAM and within a compressed address range associated with the uncompressed block when the packed word is full of non-zero data elements, or before the packed word is full if the next input word is of another uncompressed block.

公开(公告)号：US20230185451A1

公开(公告)日：2023-06-15

申请号：US17643999

申请日：2021-12-13

Applicant: Xilinx, Inc.

Inventor： Vamsi Krishna Nalluri ,  Sai Lalith Chaitanya Ambatipudi ,  Mrinal J. Sarmah ,  Rajeev Patwari ,  Shreyas Manjunath ,  Sandeep Jayant Sathe

IPC: G06F3/06

CPC classification number: G06F3/0608 ,  G06F3/064 ,  G06F3/0673

Abstract: Approaches for data compression involve a compression circuit packing non-zero data elements of a succession of words of a plurality of blocks into packed words by packing non-zero data elements of one or more words of the succession in each packed word, and restricting each packed word to data elements of one uncompressed block. The compression circuit writes each packed word in a RAM and within a compressed address range associated with the uncompressed block when the packed word is full of non-zero data elements, or before the packed word is full if the next input word is of another uncompressed block.

公开(公告)号：US11200182B1

公开(公告)日：2021-12-14

申请号：US16411500

申请日：2019-05-14

Applicant: Xilinx, Inc.

Inventor： Mrinal J. Sarmah ,  Shreyas Manjunath ,  Prasun K. Raha

IPC: G06F13/16 ,  G06F13/40 ,  G06F9/46

Abstract: A system includes a synchronizer circuit configured to monitor a first bus coupled between a memory and a first device to determine an occupancy threshold of the memory based on one or more write requests from the first device. The synchronizer circuit monitors a second bus between the memory and a second device to receive a first read transaction of a read request from the second device. The synchronizer circuit determines that the first read transaction is allowed to be sent to the memory based on the occupancy threshold of the memory. In response to the determination, the first read transaction is sent to the memory.