公开(公告)号：US5838825A

公开(公告)日：1998-11-17

申请号：US784709

申请日：1997-01-16

申请人： Yoshimasa Obayashi ,  Katsuyuki Kaneko ,  Yoshiteru Mino ,  Sadafumi Tomida

发明人： Yoshimasa Obayashi ,  Katsuyuki Kaneko ,  Yoshiteru Mino ,  Sadafumi Tomida

IPC分类号： G06T9/00 ,  G06K9/36 ,  G06K9/46

CPC分类号： G06T9/007

摘要： One block of non-zero coefficients obtained through the decoding of the entropy decoding unit 2024 is stored in the coefficient storage unit 121 in accordance with positional coordinates calculated by the non-zero coefficient scanning order calculation unit 2023a and the non-zero coefficient position conversion unit 2023b. The stored non-zero coefficients are then inverse quantized by the inverse quantization unit 2022. The non-zero coefficient range calculation unit 122 specifies a region of the coefficient storage unit 121 in which the non-zero coefficients are stored. The calculation order control unit 123 controls the inverse DCT unit 2021 to only perform an inverse DCT (discrete cosine transform) for non-zero coefficients located in the specified region.

摘要翻译： 通过熵解码单元2024的解码获得的一个非零系数块根据由非零系数扫描顺序计算单元2023a计算的位置坐标和非零系数位置转换而被存储在系数存储单元121中 单位2023b。 存储的非零系数然后由逆量化单元2022进行逆量化。非零系数范围计算单元122指定存储非零系数的系数存储单元121的区域。 计算顺序控制单元123控制逆DCT单元2021仅对位于指定区域中的非零系数执行逆DCT（离散余弦变换）。

公开(公告)号：US20050135402A1

公开(公告)日：2005-06-23

申请号：US10998136

申请日：2004-11-29

申请人： Kenichi Kawaguchi ,  Yoshiteru Mino

发明人： Kenichi Kawaguchi ,  Yoshiteru Mino

IPC分类号： G06T1/60 ,  G06F13/38 ,  H04J3/26 ,  H04N5/00 ,  H04N21/458

CPC分类号： H04N21/4583

摘要： A buffer is provided between an image processor and image I/O unit and a shared memory to be accessed by those units in common, and the buffer is controlled so as to be used only for a specific access, and data transmission to the shared memory is also controlled. With respect to a single transmission request from the image processor and a burst transmission request from the image I/O unit, a selector is controlled such that the single transmission data is retained in the buffer and that the burst transmission to the shared memory is executed.

摘要翻译： 在图像处理器和图像I / O单元之间提供缓冲器和由这些单元共享的共享存储器，并且缓冲器被控制以仅被用于特定访问，并且数据传输到共享存储器 也受到控制。 对于来自图像处理器的单个传输请求和来自图像I / O单元的突发传输请求，控制选择器使得单个传输数据保留在缓冲器中，并且执行到共享存储器的突发传输 。

公开(公告)号：US06789140B2

公开(公告)日：2004-09-07

申请号：US10214304

申请日：2002-08-08

申请人： Atsushi Kotani ,  Yoshiteru Mino

发明人： Atsushi Kotani ,  Yoshiteru Mino

IPC分类号： G06F1300

CPC分类号： G06F9/3877

摘要： The data processor for processing operation data stored in a memory connected to an external bus in the order of operations includes: an interface section for holding a parameter required for transfer of the operation data; an operation section receiving the operation data from the interface section for performing predetermined processing; and an operation memory for storing the operation data transferred. The interface section sequentially transfers the operation data from the memory connected to the external bus to the operation memory using the parameter, and sequentially transfers the operation data from the operation memory to the operation section.

摘要翻译： 用于处理按照操作顺序存储在连接到外部总线的存储器中的操作数据的数据处理器包括：用于保存传送操作数据所需的参数的接口部分; 从所述接口部接收所述操作数据以进行预定处理的操作部; 以及用于存储传送的操作数据的操作存储器。 接口部分使用该参数将操作数据从连接到外部总线的存储器顺序传送到操作存储器，并将操作数据从操作存储器顺序地传送到操作部分。

公开(公告)号：US07925928B2

公开(公告)日：2011-04-12

申请号：US11984008

申请日：2007-11-13

申请人： Yasunori Yamamoto ,  Keizo Sumida ,  Yoshiteru Mino

发明人： Yasunori Yamamoto ,  Keizo Sumida ,  Yoshiteru Mino

IPC分类号： G06F11/00

CPC分类号： G06F11/1417 ,  G06F11/1004

摘要： After power activation, a transferer 14 detects a bootstrap program 111 having a first error check code 114 assigned thereto and being stored in a first storage device 11, subjects the bootstrap program 111 to an error detection/correction process, and transfers the bootstrap program 111 to the second storage device 12. If the transfer is properly completed, by executing the bootstrap program 111 on the second storage device 12, the CPU 10 performs an error detection/correction process for a main program 112 having a second error check code 115 assigned thereto, and transfers the main program 112 to a third storage device 13, after which the CPU's control branches out to the main program 112 on the third storage device 13. As a result, system boot can be performed without employing a NOR type flash memory.

摘要翻译： 在电源激活之后，传送器14检测具有分配给其的第一错误检查码114并被存储在第一存储装置11中的自举程序111，使自举程序111进行错误检测/校正处理，并且传送引导程序111 如果传送正确完成，则通过在第二存储装置12上执行自举程序111，CPU 10对分配了第二错误检查代码115的主程序112执行错误检测/校正处理 并且将主程序112传送到第三存储装置13，之后CPU的控制分支到第三存储装置13上的主程序112.结果，可以执行系统引导而不使用NOR型闪存 。

公开(公告)号：US06927776B2

公开(公告)日：2005-08-09

申请号：US10146892

申请日：2002-05-17

申请人： Yoshiteru Mino ,  Masanori Henmi ,  Kenji Matsushita

发明人： Yoshiteru Mino ,  Masanori Henmi ,  Kenji Matsushita

IPC分类号： G06F13/40 ,  G06F13/00

CPC分类号： G06F13/405

摘要： The data transfer device for transferring data between a system bus and a local memory having a frame buffer region and a general region includes an interface section and a data processor. The interface section generates a transfer parameter for accessing one of the frame buffer region and the general region based on control data for controlling data transfer sent from the system bus and outputs the generated transfer parameter, in addition to transferring data to/from the system bus. The data processor generates an address of data to be transferred in the local memory according to the transfer parameter, and transfers data to/from the local memory using the generated address, in addition to transferring data to/from the interface section.

摘要翻译： 用于在系统总线和具有帧缓冲区域和一般区域的本地存储器之间传送数据的数据传送装置包括接口部分和数据处理器。 基于用于控制从系统总线发送的数据传送的控制数据，接口部分生成用于访问帧缓冲区域和一般区域中的一个的传送参数，并且输出生成的传送参数，以及向系统总线传送数据 。 数据处理器根据传送参数产生要在本地存储器中传送的数据的地址，并且除了从接口部分传送数据之外还使用生成的地址将数据传送到本地存储器。

公开(公告)号：US20050144430A1

公开(公告)日：2005-06-30

申请号：US11019054

申请日：2004-12-22

申请人： Yasunori Yamamoto ,  Keizo Sumida ,  Yoshiteru Mino

发明人： Yasunori Yamamoto ,  Keizo Sumida ,  Yoshiteru Mino

IPC分类号： G06F11/10 ,  G06F9/06 ,  G06F9/24 ,  G06F9/445 ,  G06F12/16

CPC分类号： G06F11/1417 ,  G06F11/1004

摘要： After power activation, a transferer 14 detects a bootstrap program 111 having a first error check code 114 assigned thereto and being stored in a first storage device 11, subjects the bootstrap program 111 to an error detection/correction process, and transfers the bootstrap program 111 to the second storage device 12. If the transfer is properly completed, by executing the bootstrap program 111 on the second storage device 12, the CPU 10 performs an error detection/correction process for a main program 112 having a second error check code 115 assigned thereto, and transfers the main program 112 to a third storage device 13, after which the CPU's control branches out to the main program 112 on the third storage device 13. As a result, system boot can be performed without employing a NOR type flash memory.

摘要翻译： 在电源激活之后，传送器14检测具有分配给其的第一错误检查码114并被存储在第一存储装置11中的自举程序111，使自举程序111进行错误检测/校正处理，并且传送引导程序111 到第二存储装置12。 如果传送正确完成，则通过在第二存储装置12上执行引导程序111，CPU10对分配有第二错误检查代码115的主程序112执行错误检测/校正处理，并且传送主程序 112到第三存储装置13，之后CPU的控制分支到第三存储装置13上的主程序112。 因此，可以在不使用NOR型闪存的情况下执行系统引导。

公开(公告)号：US06782433B2

公开(公告)日：2004-08-24

申请号：US09747685

申请日：2000-12-26

申请人： Yoshiteru Mino

发明人： Yoshiteru Mino

IPC分类号： G06F1320

CPC分类号： G06F13/28

摘要： There is provided a data transfer apparatus for transferring data from a main memory coupled to a main bus to a local memory coupled to a local bus. The data transfer apparatus includes: a first-in-first-out buffer having a data region for storing one or more words of CPU access data which is accessed by a CPU coupled to the main bus, and a plurality of words of DMA access data which is accessed by a DMA controller coupled to the main bus; and a controller for controlling the first-in-first-out buffer. When the local bus is available, the controller controls the first-in-first-out buffer so as to consecutively transfer the one or more words of CPU access data stored in the data region to the local memory, and to burst transfer the plurality of words of DMA access data stored in the data region to the local memory.

摘要翻译： 提供了一种用于将数据从耦合到主总线的主存储器传送到耦合到本地总线的本地存储器的数据传送装置。 数据传送装置包括：先进先出缓冲器，具有用于存储由与主总线耦合的CPU访问的CPU访问数据的一个或多个字的数据区域以及DMA访问数据的多个字 其由耦合到主总线的DMA控制器访问; 以及用于控制先进先出缓冲器的控制器。 当本地总线可用时，控制器控制先进先出缓冲器，以便将存储在数据区域中的CPU访问数据的一个或多个字连续传送到本地存储器，并且突发传送多个 将存储在数据区域中的DMA访问数据的字写入本地存储器。

公开(公告)号：US20120096335A1

公开(公告)日：2012-04-19

申请号：US13336647

申请日：2011-12-23

申请人： Tsukasa TAKAHASHI ,  Tomohisa Sezaki ,  Nobuhiro Tsuboi ,  Yoshiteru Mino

发明人： Tsukasa TAKAHASHI ,  Tomohisa Sezaki ,  Nobuhiro Tsuboi ,  Yoshiteru Mino

IPC分类号： G06F12/02 ,  G06F11/10 ,  H03M13/05

CPC分类号： G06F11/1402 ,  G06F11/1068 ,  G06F11/1417 ,  G06F12/0246 ,  G06F2212/7202

摘要： A read process is performed on an ith designated block storing an ith divided data string. If the ith divided data string is not normally read, the read process is sequentially executed on ith ordinary blocks each storing the ith divided data string, where the ith ordinary blocks are included in ordinary block groups, respectively. When the ith divided data string is normally read, it is determined whether or not reading p divided data strings has been completed. If it is determined that the reading the p divided data strings has not been completed, the read process is performed on an (i+1)th designated block storing an (i+1)th divided data string following the ith divided data string.

摘要翻译： 在存储第i个分割数据串的第i个指定块上执行读取处理。 如果第i个分割数据串未被正常读取，则读取处理依次执行在存储第i个分割数据串的第i个普通块上，其中第一个普通块分别包含在普通块组中。 当第i个分割数据串被正常读取时，确定是否读取p个划分的数据串已经完成。 如果确定p分割数据串的读取尚未完成，则在存储第i个分割数据串之后的第（i + 1）个划分数据串的第（i + 1）指定块上执行读取处理。

公开(公告)号：US20100090718A1

公开(公告)日：2010-04-15

申请号：US12598011

申请日：2008-06-09

申请人： Atsushi Ubukata ,  Ryuta Tsutsui ,  Masataka Osaka ,  Yoshiteru Mino ,  Tomohisa Sezaki ,  HIrotaka Doi

发明人： Atsushi Ubukata ,  Ryuta Tsutsui ,  Masataka Osaka ,  Yoshiteru Mino ,  Tomohisa Sezaki ,  HIrotaka Doi

IPC分类号： G01R31/26

CPC分类号： G01R31/3177 ,  G01R31/3187

摘要： States of LSI internal signals (100 to 107) are monitored. Signal name information (31), signal state information (32), and information (33) about time in an LSI when a signal undergoes a state transition, are packetized and output as trace information (10) to the outside. In a development supporting device, the trace information (10) is decoded, the time information of the LSI is converted into real-time information, and based on the resultant information, a waveform of an LSI internal signal is reproduced. A plurality of LSI internal signals can be traced using terminals (16) the number of which is smaller than the number of the signals to be traced.

摘要翻译： 监视LSI内部信号状态（100〜107）。 将信号状态信息（31），信号状态信息（32）以及关于信号进行状态转换时的LSI的时间的信息（33）分组化并作为跟踪信息（10）输出到外部。 在显影支持装置中，跟踪信息（10）被解码，LSI的时间信息被转换为实时信息，并且基于所得到的信息，再现LSI内部信号的波形。 可以使用其数量小于要跟踪的信号的数量的终端（16）来跟踪多个LSI内部信号。

公开(公告)号：US07543137B2

公开(公告)日：2009-06-02

申请号：US11388972

申请日：2006-03-27

申请人： Junichi Terai ,  Yasunori Yamamoto ,  Keizo Sumida ,  Yoshiteru Mino ,  Yoshinori Tokimoto

发明人： Junichi Terai ,  Yasunori Yamamoto ,  Keizo Sumida ,  Yoshiteru Mino ,  Yoshinori Tokimoto

IPC分类号： G06F9/00 ,  G06F9/24 ,  G06F13/00

CPC分类号： G06F9/4403

摘要： An information processing device is provided in which a valid initial program is transferred to a RAM while avoiding a invalid block which is present in a low reliable storage device, such as a NAND-type flash memory or the like. A management information storing section 29 stores management information 30 indicating a position of a invalid block in a first storage device 31. When an information processing device 1 is powered on, a transfer determination section 20 is controlled to read a BSP 26 from a valid block of a first storage device 11 based on the management information 30, and transfer the BSP 26 to a second storage device 32. Thereby, it is possible to avoid reading of a invalid block present in the first storage device 31.

摘要翻译： 提供一种信息处理装置，其中有效的初始程序被传送到RAM，同时避免存在于诸如NAND型闪存等的低可靠性存储装置中的无效块。 管理信息存储部分29将指示无效块的位置的管理信息30存储在第一存储装置31中。当信息处理装置1通电时，传送确定部分20被控制以从有效块读取BSP 26 基于管理信息30的第一存储装置11，并将BSP 26传送到第二存储装置32.由此，可以避免读取第一存储装置31中存在的无效块。