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    Optical semiconductor device and manufacturing method of the same
    2.
    发明申请
    Optical semiconductor device and manufacturing method of the same 有权
    光半导体器件及其制造方法

    公开(公告)号：US20100090196A1

    公开(公告)日：2010-04-15

    申请号：US12654016

    申请日：2009-12-08

    Applicant: Nami Yasuoka ,  Kenichi Kawaguchi

    Inventor： Nami Yasuoka ,  Kenichi Kawaguchi

    IPC: H01L29/66

    CPC classification number: H01L31/18 ,  B82Y20/00 ,  H01L31/0352 ,  H01L31/035236

    Abstract: A side barrier is provided between columnar dots each constituted by directly stacking respective quantum dots in seven or more layers. Out of respective side barrier layers composing the side barrier, each of the lower side barrier layers (four layers of the undermost layer to the fourth layer from the bottom) is formed as a first side barrier layer into which a tensile strain is introduced, and each of the upper side barrier layers (three layers of the fifth Layer to the uppermost layer from the bottom) is formed as a second side barrier layer which has no strain.

    Abstract translation: 在通过以7层或更多层直接层叠各量子点构成的柱状点之间设置有侧壁。 在构成侧壁的各个侧壁阻挡层中，形成作为施加拉伸应变的第一侧阻挡层，下侧阻挡层（从底部的最下层到第四层的四层） 每个上侧阻挡层（从第五层到底层的最上层三层）被形成为没有应变的第二侧阻挡层。

    Data transfer apparatus with control of buses to optimize different size data transfers
    3.
    发明授权
    Data transfer apparatus with control of buses to optimize different size data transfers 有权
    数据传输设备，可控制总线，优化不同大小的数据传输

    公开(公告)号：US07685353B2

    公开(公告)日：2010-03-23

    申请号：US12390198

    申请日：2009-02-20

    Applicant: Kenichi Kawaguchi

    Inventor： Kenichi Kawaguchi

    IPC: G06F13/36

    CPC classification number: G06F13/4027 ,  G06F13/4031 ,  G06F13/4059 ,  G06F13/423 ,  G06F2213/0024

    Abstract: A bus bridge is connected to a primary bus and a secondary bus, and relays data between a master and a target which are each connected to a different one of the primary and secondary buses. The bus bridge includes a primary bus interface, a secondary bus interface, a data FIFO, and a register block. The register block, which can be written by the master, includes two registers corresponding to the primary and secondary buses. Relay information showing the number of entries of data to be relayed from the target to the master is registered in a register corresponding to a bus to which the target is connected. In a read transaction, the primary bus interface or the secondary bus interface reads data from the target until data of the amount shown by the registered relay information is stored in the data FIFO.

    Abstract translation: 总线桥连接到主总线和辅助总线，并且中继主机和目标之间的数据，每个主站和目标站之间连接到主总线和次总线之间的不同的总线。 总线桥包括主总线接口，辅助总线接口，数据FIFO和寄存器块。 可由主器件写入的寄存器块包括与主母线和辅助母线相对应的两个寄存器。 显示要从目标到主机中继的数据的条目数的中继信息被登记在对应于目标连接到的总线的寄存器中。 在读取事务中，主总线接口或辅助总线接口从目标读取数据，直到被注册的中继信息所示量的数据被存储在数据FIFO中。

    Bus bridge arbitration method
    4.
    发明授权
    Bus bridge arbitration method 有权
    总线桥仲裁方法

    公开(公告)号：US07313642B2

    公开(公告)日：2007-12-25

    申请号：US10391167

    申请日：2003-03-18

    Applicant: Kenichi Kawaguchi

    Inventor： Kenichi Kawaguchi

    IPC: G06F13/36

    CPC classification number: G06F13/4031

    Abstract: A bus bridge is connected to a first bus and a second bus. In the bus bridge, an arbiter grants ownership of the first bus to one of a plurality of devices connected to the first bus. A detecting unit detects a read cycle initiated by the device on the first bus to read data from a memory which is also accessible by another device connected to the second bus. A first signaling unit sends a first signal to the arbiter, when the data is not yet transferable to the device when the read cycle is detected. A second signaling unit sends a second signal to the arbiter, when the data becomes transferable to the device. The arbiter deprives the device of the ownership of the first bus upon receipt of the first signal, and withholds from granting the ownership to the device until receipt of the second signal.

    Abstract translation: 总线桥连接到第一总线和第二总线。 在总线桥中，仲裁者将第一总线的所有权授予连接到第一总线的多个设备之一。 检测单元检测由第一总线上的设备发起的读周期，以从存储器读取数据，该存储器也可由连接到第二总线的另一设备访问。 当检测到读取周期时，当数据不能传输到设备时，第一信令单元向仲裁器发送第一信号。 当数据可转移到设备时，第二信令单元向仲裁器发送第二信号。 仲裁者在收到第一个信号后，剥夺了第一个公共汽车的所有权，并将所有权授予设备，直到收到第二个信号。

    Bus bridge with stored controlling relay information
    6.
    发明授权
    Bus bridge with stored controlling relay information 有权
    具有存储控制继电器信息的总线桥

    公开(公告)号：US07185137B2

    公开(公告)日：2007-02-27

    申请号：US11209511

    申请日：2005-08-23

    Applicant: Kenichi Kawaguchi

    Inventor： Kenichi Kawaguchi

    IPC: G06F13/36

    CPC classification number: G06F13/4027 ,  G06F13/4031 ,  G06F13/4059 ,  G06F13/423 ,  G06F2213/0024

    Abstract: A bus bridge is connected to a primary bus and a secondary bus, and relays data between a master and a target which are each connected to a different one of the primary and secondary buses. The bus bridge includes a primary bus interface, a secondary bus interface, a data FIFO, and a register block. The register block, which can be written by the master, includes two registers corresponding to the primary and secondary buses. Relay information showing the number of entries of data to be relayed from the target to the master is registered in a register corresponding to a bus to which the target is connected. In a read transaction, the primary bus interface or the secondary bus interface reads data from the target until data of the amount shown by the registered relay information is stored in the data FIFO.

    Abstract translation: 总线桥连接到主总线和辅助总线，并且中继主机和目标之间的数据，每个主站和目标站之间连接到主总线和次总线之间的不同的总线。 总线桥包括主总线接口，辅助总线接口，数据FIFO和寄存器块。 可由主器件写入的寄存器块包括与主母线和辅助母线相对应的两个寄存器。 显示要从目标到主机中继的数据的条目数的中继信息被登记在对应于目标连接到的总线的寄存器中。 在读取事务中，主总线接口或辅助总线接口从目标读取数据，直到被注册的中继信息所示量的数据被存储在数据FIFO中。

    Bus bridge
    7.
    发明申请
    Bus bridge 有权

    公开(公告)号：US20060047882A1

    公开(公告)日：2006-03-02

    申请号：US11209511

    申请日：2005-08-23

    Applicant: Kenichi Kawaguchi

    Inventor： Kenichi Kawaguchi

    IPC: G06F13/36

    CPC classification number: G06F13/4027 ,  G06F13/4031 ,  G06F13/4059 ,  G06F13/423 ,  G06F2213/0024

    Abstract: A bus bridge is connected to a primary bus and a secondary bus, and relays data between a master and a target which are each connected to a different one of the primary and secondary buses. The bus bridge includes a primary bus interface, a secondary bus interface, a data FIFO, and a register block. The register block, which can be written by the master, includes two registers corresponding to the primary and secondary buses. Relay information showing the number of entries of data to be relayed from the target to the master is registered in a register corresponding to a bus to which the target is connected. In a read transaction, the primary bus interface or the secondary bus interface reads data from the target until data of the amount shown by the registered relay information is stored in the data FIFO.

    Data transfer apparatus
    10.
    发明申请
    Data transfer apparatus 审中-公开
    数据传输装置

    公开(公告)号：US20050135402A1

    公开(公告)日：2005-06-23

    申请号：US10998136

    申请日：2004-11-29

    Applicant: Kenichi Kawaguchi ,  Yoshiteru Mino

    Inventor： Kenichi Kawaguchi ,  Yoshiteru Mino

    IPC: G06T1/60 ,  G06F13/38 ,  H04J3/26 ,  H04N5/00 ,  H04N21/458

    CPC classification number: H04N21/4583

    Abstract: A buffer is provided between an image processor and image I/O unit and a shared memory to be accessed by those units in common, and the buffer is controlled so as to be used only for a specific access, and data transmission to the shared memory is also controlled. With respect to a single transmission request from the image processor and a burst transmission request from the image I/O unit, a selector is controlled such that the single transmission data is retained in the buffer and that the burst transmission to the shared memory is executed.

    Abstract translation: 在图像处理器和图像I / O单元之间提供缓冲器和由这些单元共享的共享存储器，并且缓冲器被控制以仅被用于特定访问，并且数据传输到共享存储器 也受到控制。 对于来自图像处理器的单个传输请求和来自图像I / O单元的突发传输请求，控制选择器使得单个传输数据保留在缓冲器中，并且执行到共享存储器的突发传输 。

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