公开(公告)号：US08817521B2

公开(公告)日：2014-08-26

申请号：US13488937

申请日：2012-06-05

申请人： Yu-Sheng Chen ,  Heng-Yuan Lee ,  Yen-Ya Hsu ,  Pang-Shiu Chen ,  Ching-Chih Hsu ,  Frederick T. Chen

发明人： Yu-Sheng Chen ,  Heng-Yuan Lee ,  Yen-Ya Hsu ,  Pang-Shiu Chen ,  Ching-Chih Hsu ,  Frederick T. Chen

IPC分类号： G11C11/00

CPC分类号： G11C13/0069 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0064 ,  G11C2013/0071 ,  G11C2013/0073 ,  G11C2213/79

摘要： A control method for at least one memory cell is disclosed. The memory cell includes a transistor and a resistor. The resistor is connected to the transistor in series between a first node and a second node. In a programming mode, the memory cell is programmed. When it is determined that the memory cell has been successfully programmed, impedance of the memory cell is in a first state. When it is determined that the memory cell has not been successfully programmed, a specific action is executed to reset the memory cell. The impedance of the memory cell is in a second state after the step resetting the memory cell. The impedance of the memory cell in the second state is higher than that of the memory cell in the first state.

摘要翻译： 公开了至少一个存储单元的控制方法。 存储单元包括晶体管和电阻器。 电阻器在第一节点和第二节点之间串联连接到晶体管。 在编程模式下，存储单元被编程。 当确定存储器单元已被成功编程时，存储器单元的阻抗处于第一状态。 当确定存储器单元未成功编程时，执行特定动作来重置存储器单元。 在步骤重置存储单元之后，存储单元的阻抗处于第二状态。 第二状态下的存储单元的阻抗高于第一状态下的存储单元的阻抗。

公开(公告)号：US08223528B2

公开(公告)日：2012-07-17

申请号：US12649286

申请日：2009-12-29

申请人： Yu-Sheng Chen ,  Heng-Yuan Lee ,  Yen-Ya Hsu ,  Pang-Shiu Chen ,  Ching-Chih Hsu

发明人： Yu-Sheng Chen ,  Heng-Yuan Lee ,  Yen-Ya Hsu ,  Pang-Shiu Chen ,  Ching-Chih Hsu

IPC分类号： G11C11/00

CPC分类号： G11C13/0069 ,  G11C13/0064 ,  G11C2013/0071 ,  G11C2013/0073 ,  G11C2213/79

摘要： A control method for at least one memory cell is disclosed. The memory cell includes a transistor and a resistor. The resistor is connected to the transistor between a first node and a second node. In a programming mode, the memory cell is programmed. The step of programming the memory cell includes providing a first controlling voltage to a gate of the transistor, providing a first setting voltage to the first node, and providing a second setting voltage to the second node. When it is determined that the memory cell has been successfully programmed, a specific action is executed.

摘要翻译： 公开了至少一个存储单元的控制方法。 存储单元包括晶体管和电阻器。 电阻器连接到第一节点和第二节点之间的晶体管。 在编程模式下，存储单元被编程。 编程存储单元的步骤包括向晶体管的栅极提供第一控制电压，向第一节点提供第一设定电压，并向第二节点提供第二设定电压。 当确定存储器单元已被成功编程时，执行特定动作。

公开(公告)号：US20100102306A1

公开(公告)日：2010-04-29

申请号：US12335538

申请日：2008-12-16

申请人： Yen-Ya Hsu ,  Chih-Wei Chen

发明人： Yen-Ya Hsu ,  Chih-Wei Chen

IPC分类号： H01L29/18 ,  G11C11/00 ,  H01L21/02

CPC分类号： G11C11/5678 ,  G11C11/5685 ,  G11C13/0004 ,  G11C13/0007 ,  G11C2213/32 ,  H01L45/04 ,  H01L45/145

摘要： A multi-level memory cell having a bottom electrode, a first dielectric layer, a plurality of memory material layers, a plurality of second dielectric layers, and an upper electrode is provided. The bottom electrode is disposed in a substrate. The first dielectric layer is disposed on the substrate and has an opening exposing the bottom electrode. The memory material layers are stacked on a sidewall of the first dielectric layer exposed by the opening and are electrically connected to the bottom electrode. The second dielectric layers are respectively disposed between every adjacent two memory material layers and are located on the sidewall of the first dielectric layer. The upper electrode is disposed on the memory material layers. A manufacturing method of the multi-level memory cell is further provided. A multi-bit data can be stored in a single memory cell, and both the process complexity and the cost are reduced.

摘要翻译： 提供具有底部电极，第一电介质层，多个存储材料层，多个第二电介质层和上部电极的多层存储单元。 底部电极设置在基板中。 第一电介质层设置在基板上，并且具有暴露底部电极的开口。 存储材料层层叠在由开口暴露的第一电介质层的侧壁上，并与底部电极电连接。 第二电介质层分别设置在每个相邻的两个存储材料层之间，并且位于第一介电层的侧壁上。 上电极设置在记忆材料层上。 还提供了多级存储单元的制造方法。 多位数据可以存储在单个存储器单元中，并且减少了处理复杂性和成本。

公开(公告)号：US08067766B2

公开(公告)日：2011-11-29

申请号：US12335538

申请日：2008-12-16

申请人： Yen-Ya Hsu ,  Chih-Wei Chen

发明人： Yen-Ya Hsu ,  Chih-Wei Chen

IPC分类号： H01L29/08

CPC分类号： G11C11/5678 ,  G11C11/5685 ,  G11C13/0004 ,  G11C13/0007 ,  G11C2213/32 ,  H01L45/04 ,  H01L45/145

摘要： A multi-level memory cell having a bottom electrode, a first dielectric layer, a plurality of memory material layers, a plurality of second dielectric layers, and an upper electrode is provided. The bottom electrode is disposed in a substrate. The first dielectric layer is disposed on the substrate and has an opening exposing the bottom electrode. The memory material layers are stacked on a sidewall of the first dielectric layer exposed by the opening and are electrically connected to the bottom electrode. The second dielectric layers are respectively disposed between every adjacent two memory material layers and are located on the sidewall of the first dielectric layer. The upper electrode is disposed on the memory material layers. A manufacturing method of the multi-level memory cell is further provided. A multi-bit data can be stored in a single memory cell, and both the process complexity and the cost are reduced.

摘要翻译： 提供具有底部电极，第一电介质层，多个存储材料层，多个第二电介质层和上部电极的多层存储单元。 底部电极设置在基板中。 第一电介质层设置在基板上，并且具有暴露底部电极的开口。 存储材料层层叠在由开口暴露的第一电介质层的侧壁上，并与底部电极电连接。 第二电介质层分别设置在每个相邻的两个存储材料层之间，并且位于第一介电层的侧壁上。 上电极设置在记忆材料层上。 还提供了多级存储单元的制造方法。 多位数据可以存储在单个存储器单元中，并且减少了处理复杂性和成本。