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    INTEGRATED CIRCUIT AND OPERATION METHOD OF SERIALIZER/DESERIALIZER PHYSICAL LAYER CIRCUIT THEREOF
    91.
    发明申请
    INTEGRATED CIRCUIT AND OPERATION METHOD OF SERIALIZER/DESERIALIZER PHYSICAL LAYER CIRCUIT THEREOF 有权

    公开(公告)号：US20170154002A1

    公开(公告)日：2017-06-01

    申请号：US15001196

    申请日：2016-01-19

    Applicant: Faraday Technology Corp.

    Inventor： Yuan-Min Hu ,  Yin-Fu Lin ,  Shan-Chih Wen

    IPC: G06F13/40

    CPC classification number: G06F13/4068

    Abstract: An integrated circuit and an operation method of a SERDES PHY layer circuit thereof are provided. When the SERDES PHY layer circuit is in a calibration preparation state and a signal of a first calibration input pin is an enable state, or when the SERDES PHY layer circuit is in the calibration preparation state, and signals of first and second calibration input pins are in the enable state, the SERDES PHY layer circuit enters a calibration state (using a reference resistor for current calibration). After the current calibration is completed, the SERDES PHY layer circuit enters a calibration completion state (without using the reference resistor and connecting the first calibration input pin to the first calibration output pin). The SERDES PHY layer circuit sets the signal of the first calibration output pin to a disable state when the SERDES PHY layer circuit is not in the calibration completion state.

    Method and apparatus for detecting noise of audio signals
    92.
    发明授权
    Method and apparatus for detecting noise of audio signals 有权
    用于检测音频信号噪声的方法和装置

    公开(公告)号：US09431024B1

    公开(公告)日：2016-08-30

    申请号：US14731432

    申请日：2015-06-05

    Applicant: Faraday Technology Corp.

    Inventor： Chung-Chi Hsu

    IPC: G10L21/02 ,  G10L21/034 ,  G10L19/02 ,  G10L21/0264 ,  G10L21/0232

    CPC classification number: G10L25/84 ,  G10L21/0216 ,  G10L21/0232

    Abstract: A method and an apparatus for detecting noise of audio signals are provided. The method includes steps of converting an audio signal into a plurality of audio frames, where the audio frames are arranged in chronological order while taking a target frame as a center, calculating a plurality of magnitudes respectively corresponding to a plurality of spectral components of each of the audio frames, calculating differences between the adjacent magnitudes in a time-frequency domain to obtain a plurality of difference values in at least two directions orthogonal to each other in the time-frequency domain, where the time-frequency domain is defined by the audio frames, determining a maximum degree of difference of the magnitudes in the time-frequency domain according to the difference values, and determining whether a part of the audio signal corresponding to the target frame is a noise according to the maximum degree of difference.

    Abstract translation: 提供了一种用于检测音频信号噪声的方法和装置。 该方法包括以下步骤：将音频信号转换成多个音频帧，其中音频帧按照时间顺序排列，同时以目标帧为中心，计算分别对应于每个的多个频谱分量的多个量值 音频帧，计算时间 - 频域中的相邻量值之间的差异，以在时间 - 频率域中彼此正交的至少两个方向上获得多个差值，其中时间 - 频域由音频 根据差值确定时频域中的幅度的最大差异度，并且根据最大差异度来确定与目标帧对应的音频信号的一部分是否为噪声。

    Static memory apparatus and data reading method thereof
    94.
    发明授权
    Static memory apparatus and data reading method thereof 有权
    静态存储装置及其数据读取方法

    公开(公告)号：US09240228B1

    公开(公告)日：2016-01-19

    申请号：US14457125

    申请日：2014-08-12

    Applicant: Faraday Technology Corp.

    Inventor： Biao Chen ,  Zhao-Yong Zhang ,  Hao Wu ,  Kun-Ti Lee

    IPC: G11C7/04 ,  G11C7/12 ,  G11C7/06

    CPC classification number: G11C7/12 ,  G11C7/06 ,  G11C7/14 ,  G11C11/419

    Abstract: A static memory apparatus and a data reading method thereof are provided. The static memory apparatus includes a plurality of memory cells, a plurality of dummy memory cells, a sense amplifier, and a discharge current adjuster. The dummy memory cells respectively include a plurality discharge ends for discharging charges on a dummy bit line. The sense amplifier is enabled for a sensing and amplifying operation according to a signal on the dummy bit line, and the sense amplifier generates readout data accordingly. The discharge current adjuster adjusts at least one discharge current on at least one controlled discharge end according to an operating voltage of the memory cells.

    Abstract translation: 提供了一种静态存储装置及其数据读取方法。 静态存储装置包括多个存储单元，多个虚拟存储单元，读出放大器和放电电流调节器。 虚拟存储单元分别包括用于在虚拟位线上放电的多个放电端。 读出放大器根据虚拟位线上的信号被使能用于感测和放大操作，并且读出放大器相应地产生读出数据。 放电电流调节器根据存储单元的工作电压在至少一个受控放电端调节至少一个放电电流。

    Method of synchronizing dual clock frequencies
    95.
    发明申请
    Method of synchronizing dual clock frequencies 有权
    同步双时钟频率的方法

    公开(公告)号：US20040199802A1

    公开(公告)日：2004-10-07

    申请号：US10455372

    申请日：2003-06-06

    Applicant: Faraday Technology Corp.

    Inventor： Chih-Wen Lin

    IPC: G06F001/12

    CPC classification number: G06F1/12 ,  H03L7/16

    Abstract: A higher frequency clock and a lower frequency clock are locked at a predetermined phase relationship. A total number of pulses of the higher frequency clock occurring between two sequential rising edges of the lower frequency are calculated. A count start signal is generated in response to a rising edge of the lower frequency clock. A value of a lower frequency clock count is set in response to the count start signal. The value of the lower frequency clock decrements in accordance with a frequency of the higher frequency clock. When the value of the lower frequency clock has decreased by the total number of pulses of the higher frequency clock occurring between two consecutive rising edges of the lower frequency minus 1, a synchronization signal is generated for indicating occurrence of the predetermined phase relationship between the higher frequency clock and the lower frequency clock.

    Abstract translation: 较高频率时钟和较低频率时钟被锁定在预定的相位关系。 计算在较低频率的两个连续上升沿之间出现的较高频率时钟的总脉冲数。 响应于较低频率时钟的上升沿产生计数开始信号。 响应于计数开始信号设置较低频率时钟计数的值。 较低频率时钟的值根据较高频率时钟的频率递减。 当较低频率时钟的值减小了在较低频率的两个连续上升沿之间出现的较高频率时钟的总脉冲数减1时，产生同步信号以指示较高频率时钟之间的预定相位关系的出现 频率时钟和较低频率时钟。

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