中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

103 records (took 0.018 seconds)

    Controlling Access To A Cache Memory Using Privilege Level Information
    91.
    发明申请
    Controlling Access To A Cache Memory Using Privilege Level Information 有权
    控制使用特权级别信息访问缓存内存

    公开(公告)号：US20110153926A1

    公开(公告)日：2011-06-23

    申请号：US12645788

    申请日：2009-12-23

    Applicant: Zhen Fang ,  Li Zhao ,  Ravishankar Iyer ,  Tong Li ,  Donald K. Newell

    Inventor： Zhen Fang ,  Li Zhao ,  Ravishankar Iyer ,  Tong Li ,  Donald K. Newell

    IPC: G06F12/00 ,  G06F12/08

    CPC classification number: G06F12/0895 ,  G06F12/1491 ,  Y02D10/13

    Abstract: In one embodiment, a cache memory includes entries each to store a ring level identifier, which may indicate a privilege level of information stored in the entry. This identifier may be used in performing read accesses to the cache memory. As an example, a logic coupled to the cache memory may filter an access to one or more ways of a selected set of the cache memory based at least in part on a current privilege level of a processor and the ring level identifier of the one or more ways. Other embodiments are described and claimed.

    Abstract translation: 在一个实施例中，高速缓冲存储器包括各自存储环电平标识符的条目，其可以指示存储在条目中的信息的权限级别。 该标识符可用于执行对高速缓冲存储器的读取访问。 作为示例，耦合到高速缓存存储器的逻辑可以至少部分地基于处理器的当前特权级别和一个或多个高速缓冲存储器的环电平标识符来过滤对所选择的高速缓冲存储器组的一种或多种方式的访问， 更多的方式 描述和要求保护其他实施例。

    AUTOMATICALLY USING SUPERPAGES FOR STACK MEMORY ALLOCATION
    95.
    发明申请
    AUTOMATICALLY USING SUPERPAGES FOR STACK MEMORY ALLOCATION 审中-公开
    自动使用SUPERPAGES进行堆叠内存分配

    公开(公告)号：US20100332788A1

    公开(公告)日：2010-12-30

    申请号：US12495509

    申请日：2009-06-30

    Applicant: LI ZHAO ,  Zhen Fang ,  Ravishankar Iyer ,  Donald Newell

    Inventor： LI ZHAO ,  Zhen Fang ,  Ravishankar Iyer ,  Donald Newell

    IPC: G06F12/10 ,  G06F12/00

    CPC classification number: G06F12/1027 ,  G06F2212/652

    Abstract: In one embodiment, the present invention includes a page fault handler to create page table entries and TLB entries in response to a page fault, the page fault handler to determine if a page fault resulted from a stack access, to create a superpage table entry if the page fault did result from a stack access, and to create a TLB entry for the superpage. Other embodiments are described and claimed.

    Abstract translation: 在一个实施例中，本发明包括页面错误处理程序，以响应于页面错误来创建页面表项和TLB条目，页面错误处理程序来确定页面错误是否由堆栈访问导致，以创建超级页面表项 页面错误确实来自堆栈访问，并为超级页面创建一个TLB条目。 描述和要求保护其他实施例。

    Delegating A Poll Operation To Another Device
    96.
    发明申请
    Delegating A Poll Operation To Another Device 有权
    将投票操作委托给另一个设备

    公开(公告)号：US20100318693A1

    公开(公告)日：2010-12-16

    申请号：US12482614

    申请日：2009-06-11

    Applicant: Michael J. Espig ,  Zhen Fang ,  Ravishankar Iyer ,  David J. Harriman

    Inventor： Michael J. Espig ,  Zhen Fang ,  Ravishankar Iyer ,  David J. Harriman

    IPC: G06F3/00

    CPC classification number: G06F13/24 ,  G06F9/542

    Abstract: In one embodiment, the present invention includes a method for handling a registration message received from a host processor, where the registration message delegates a poll operation with respect to a device from the host processor to another component. Information from the message may be stored in a poll table, and the component may send a read request to poll the device and report a result of the poll to the host processor based on a state of the device. Other embodiments are described and claimed.

    Abstract translation: 在一个实施例中，本发明包括一种用于处理从主机处理器接收的注册消息的方法，其中所述注册消息将关于设备的轮询操作从主机处理器委托给另一个组件。 来自消息的信息可以存储在轮询表中，并且组件可以发送读请求以轮询该设备并且基于该设备的状态向轮询处理器报告轮询的结果。 描述和要求保护其他实施例。

    Selective storage of data in levels of a cache memory
    98.
    发明授权
    Selective storage of data in levels of a cache memory 失效
    在高速缓冲存储器的级别中选择性地存储数据

    公开(公告)号：US07596662B2

    公开(公告)日：2009-09-29

    申请号：US11513554

    申请日：2006-08-31

    Applicant: Srihari Makineni ,  Jaideep Moses ,  Ravishankar Iyer ,  Ramesh Illikkal ,  Don Newell ,  Li Zhao

    Inventor： Srihari Makineni ,  Jaideep Moses ,  Ravishankar Iyer ,  Ramesh Illikkal ,  Don Newell ,  Li Zhao

    IPC: G06F12/00

    CPC classification number: G06F12/0897 ,  G06F12/128

    Abstract: In one embodiment, the present invention includes a method for incrementing a counter value associated with a cache line if the cache line is inserted into a first level cache, and storing the cache line into a second level cache coupled to the first level cache or a third level cache coupled to the second level cache based on the counter value, after eviction from the first level cache. Other embodiments are described and claimed.

    Abstract translation: 在一个实施例中，本发明包括一种用于在高速缓存行插入到第一级高速缓存中时递增与高速缓存线相关联的计数器值的方法，并且将高速缓存行存储到耦合到第一级高速缓存的第二级高速缓存或 在从第一级高速缓存驱逐之后，基于计数器值耦合到第二级高速缓存的第三级缓存。 描述和要求保护其他实施例。

    Priority based throttling for power/performance Quality of Service
    99.
    发明申请
    Priority based throttling for power/performance Quality of Service 有权
    基于优先级的电源/性能调节服务质量

    公开(公告)号：US20080250415A1

    公开(公告)日：2008-10-09

    申请号：US11786019

    申请日：2007-04-09

    Applicant: Ramesh Kumar Illikkal ,  Ravishankar Iyer ,  Jaideep Moses ,  Don Newell ,  Tryggve Fossum

    Inventor： Ramesh Kumar Illikkal ,  Ravishankar Iyer ,  Jaideep Moses ,  Don Newell ,  Tryggve Fossum

    IPC: G06F9/46

    CPC classification number: G06F9/5077 ,  G06F9/5094 ,  G06F2209/504 ,  Y02D10/22 ,  Y02D10/36

    Abstract: A method and apparatus for throttling power and/or performance of processing elements based on a priority of software entities is herein described. Priority aware power management logic receives priority levels of software entities and modifies operating points of processing elements associated with the software entities accordingly. Therefore, in a power savings mode, processing elements executing low priority applications/tasks are reduced to a lower operating point, i.e. lower voltage, lower frequency, throttled instruction issue, throttled memory accesses, and/or less access to shared resources. In addition, utilization logic potentially trackes utilization of a resource per priority level, which allows the power manager to determine operating points based on the effect of each priority level on each other from the perspective of the resources themselves. Moreover, a software entity itself may assign operating points, which the power manager enforces.

    Abstract translation: 这里描述了一种基于软件实体的优先级来节制处理元件的功率和/或性能的方法和装置。 优先级感知功率管理逻辑接收软件实体的优先级，并相应地修改与软件实体相关联的处理元件的工作点。 因此，在省电模式中，执行低优先级应用/任务的处理元件被降低到较低的工作点，即较低的电压，较低的频率，节流的指令问题，节流的存储器访问和/或较少的对共享资源的访问。 此外，利用逻辑潜在地追踪每个优先级别的资源的利用率，这允许电力管理者从资源本身的角度基于每个优先级的影响来确定工作点。 此外，软件实体本身可以分配功率管理器执行的操作点。

    Applying quality of service (QoS) to a translation lookaside buffer (TLB)
    100.
    发明申请
    Applying quality of service (QoS) to a translation lookaside buffer (TLB) 有权
    将服务质量（QoS）应用于翻译后备缓冲区（TLB）

    公开(公告)号：US20080235487A1

    公开(公告)日：2008-09-25

    申请号：US11726316

    申请日：2007-03-21

    Applicant: Ramesh Illikkal ,  Hari Kannan ,  Ravishankar Iyer ,  Donald Newell ,  Jaideep Moses ,  Li Zhao

    Inventor： Ramesh Illikkal ,  Hari Kannan ,  Ravishankar Iyer ,  Donald Newell ,  Jaideep Moses ,  Li Zhao

    IPC: G06F9/34

    CPC classification number: G06F12/126

    Abstract: In one embodiment, the present invention includes a translation lookaside buffer (TLB) having storage locations each including a priority indicator field to store a priority level associated with an agent that requested storage of the data in the TLB, and an identifier field to store an identifier of the agent, where the TLB is apportioned according to a plurality of priority levels. Other embodiments are described and claimed.

    Abstract translation: 在一个实施例中，本发明包括具有存储位置的翻译后备缓冲器（TLB），每个存储位置包括优先级指示符字段以存储与请求TLB中的数据存储的代理相关联的优先级，以及存储 代理商的标识符，其中TLB根据多个优先级分摊。 描述和要求保护其他实施例。

Patent Agency Ranking