公开(公告)号：US5317726A

公开(公告)日：1994-05-31

申请号：US722609

申请日：1991-06-26

申请人： Robert W. Horst

发明人： Robert W. Horst

IPC分类号： G06F9/52 ,  G06F11/00 ,  G06F11/10 ,  G06F11/14 ,  G06F11/16 ,  G06F11/18 ,  G06F11/20 ,  G06F15/17 ,  G11C29/00 ,  G06F9/00

CPC分类号： G06F11/185 ,  G06F11/0724 ,  G06F11/1658 ,  G06F11/1666 ,  G06F11/1683 ,  G06F11/1687 ,  G06F11/1691 ,  G06F11/2017 ,  G06F15/17 ,  G06F11/0757 ,  G06F11/10 ,  G06F11/1008 ,  G06F11/1405 ,  G06F11/1415 ,  G06F11/1645 ,  G06F11/1679 ,  G06F11/181 ,  G06F11/182 ,  G06F11/20 ,  G06F11/2007 ,  G06F11/2015 ,  G06F2201/85 ,  G11C29/74

摘要： A fault-tolerant computer system employs multiple identical CPUs executing the same instruction stream, each with their own independent memory. The multiple CPUs are loosely synchronized, as by counting events such as operating cycles and stalling any CPU ahead of others. Data output references via separate busses are voted at separate ports of each of the CPUs by voting circuits which detect when all CPUs have made the same reference, and only then pass on identical references to external I/O busses. The ports may include FIFO buffers to allow output references from the asynchronous CPUs to be handled as the CPUs load the FIFOs at different times. Input data to the CPUs from the I/O busses is not voted, but is buffered to allow the CPUs to accept it at their own clock rate.

摘要翻译： 容错计算机系统使用执行相同指令流的多个相同的CPU，每个具有它们自己的独立存储器。 多个CPU松动同步，例如通过对诸如操作周期等事件进行计数，并将任何CPU拖到其他CPU之前。 通过单独的总线的数据输出参考通过投票电路在每个CPU的不同端口上进行投票，这些电路检测所有CPU是否已经做出相同的参考，并且仅在相同的引用上传递给外部I / O总线。 端口可以​​包括FIFO缓冲器，以便在CPU在不同时间加载FIFO时允许来自异步CPU的输出引用被处理。 从I / O总线向CPU输入数据不被投票，但被缓存以允许CPU以其自己的时钟速率接受它。

公开(公告)号：US5239641A

公开(公告)日：1993-08-24

申请号：US657990

申请日：1991-02-20

申请人： Robert W. Horst

发明人： Robert W. Horst

IPC分类号： G06F11/18 ,  G06F9/52 ,  G06F11/16 ,  G06F15/17 ,  G11C29/00

CPC分类号： G06F11/184 ,  G06F11/1658 ,  G06F11/1666 ,  G06F11/1683 ,  G06F11/1687 ,  G06F11/1691 ,  G06F15/17 ,  G06F11/1679 ,  G06F11/185 ,  G06F11/20 ,  G11C29/74

摘要： A method and apparatus for synchronizing a plurality of processors. Each processor runs off of its own independent clock, indicates the occurrence of a prescribed process or event on one line and receives signals on another line for initiating a processor wait state. Each processor has a counter which counts the number of processor events indicated since the last time the processors were synchronized. When an event requiring synchronization is detected by a sync logic circuit associated with the processor, the sync logic circuit generates the wait signal after the next processor event. A compare circuit associated with each processor then tests the other event counters in the system and determines whether its associated processor is behind the others. If so, the sync logic circuit removes the wait signal until the next processor event. The processor is finally stopped when its event counter matches the event counter for the fastest processor. At that time, all processors are synchronized and may be restarted for servicing the event. If no synchronizing event occurs before an event counter reaches its maximum value, and overflow of the event counter forces resynchronization. A cycle counter is provided for counting the number of clock cycles since the last processor event. The cycle counter is set to overflow and force resynchronization at a point before maximum interrupt latency time is exceeded.

摘要翻译： 一种用于同步多个处理器的方法和装置。 每个处理器运行自己独立的时钟，指示在一条线上发生规定的处理或事件，并在另一条线路上接收信号以启动处理器等待状态。 每个处理器都有一个计数器，用于计数上次处理器同步后指示的处理器事件数。 当与处理器相关联的同步逻辑电路检测到需要同步的事件时，同步逻辑电路在下一个处理器事件之后产生等待信号。 与每个处理器相关联的比较电路然后测试系统中的其他事件计数器，并确定其关联的处理器是否在其他处理器之后。 如果是这样，同步逻辑电路去除等待信号直到下一个处理器事件。 当其事件计数器与最快处理器的事件计数器匹配时，处理器终止停止。 当时，所有处理器都是同步的，可能会重新启动以维护事件。 如果在事件计数器达到其最大值之前没有发生同步事件，并且事件计数器的溢出强制重新同步。 提供了一个周期计数器，用于对自上一个处理器事件以来的时钟周期数进行计数。 周期计数器设置为溢出，并强制在超过最大中断延迟时间之前的一点重新同步。

公开(公告)号：US5072364A

公开(公告)日：1991-12-10

申请号：US356316

申请日：1989-05-24

申请人： Robert L. Jardine ,  Shannon J. Lynch ,  Philip R. Manela ,  Robert W. Horst

发明人： Robert L. Jardine ,  Shannon J. Lynch ,  Philip R. Manela ,  Robert W. Horst

IPC分类号： G06F9/38

CPC分类号： G06F9/3861 ,  G06F9/3844 ,  G06F9/3853

摘要： A branch recovery mechanism completes the processing of a concurrently issued family of instructions depending on the location of the branch instruction in the family and on whether the branch was correctly predicted. If the branch was not correctly predicted, the writes and stores of instructions in the family the precede the branch instruction are completed and those instructions are retired. However, the writes and stores of the instructions in the family following the branch instruction are inhibited.

公开(公告)号：US4800486A

公开(公告)日：1989-01-24

申请号：US537877

申请日：1983-09-29

申请人： Robert W. Horst ,  Shannon J. Lynch ,  Cirillo L. Costantino ,  John M. Beirne

发明人： Robert W. Horst ,  Shannon J. Lynch ,  Cirillo L. Costantino ,  John M. Beirne

IPC分类号： G06F7/00 ,  G06F9/30 ,  G06F9/38 ,  G06F9/28

CPC分类号： G06F9/3885 ,  G06F9/3897

摘要： The various functional units which comprise a central processing unit of a computer are organized so as to enable a main arithmetic logic unit and special function units including an auxilliary arithmetic logic unit to access data registers, literal constants, and data from a memory cache. A general purpose bus closely couples the functional units to the main data paths and allows the CPU sequencer to branch on numerous conditions which may be indicated via test lines. Parity from the functional units is sent to clock cycle later than results in order that the parity path does not affect machine cycle time. The architecture allows unused microcode options to be used to check for correct CPU operation by halting CPU operation on a miscompare of two buses.

摘要翻译： 包括计算机的中央处理单元的各种功能单元被组织以使主算术逻辑单元和包括辅助运算逻辑单元的特殊功能单元能够访问数据寄存器，文字常数和来自存储器高速缓存的数据。 通用总线将功能单元紧密耦合到主数据路径，并允许CPU定序器在可以通过测试线指示的许多条件下分支。 来自功能单元的奇偶校验被发送到比结果更晚的时钟周期，以便奇偶校验路径不影响机器周期时间。 该体系结构允许未使用的微代码选项用于通过停止两个总线错误的CPU操作来检查正确的CPU操作。