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公开(公告)号：US20070260409A1
公开(公告)日：2007-11-08
申请号：US11777370
申请日：2007-07-13
申请人： David Boerstler , Eskinder Hailu , Jieming Qi
发明人： David Boerstler , Eskinder Hailu , Jieming Qi
IPC分类号： G06F19/00
CPC分类号： G01R29/02 , G01R31/2884
摘要： A mechanism for measuring duty cycle of a signal under test in an integrated circuit device, such as a microprocessor or system-on-a-chip is provided. The mechanism generates a frequency which is proportional to the duty cycle and which can be measured using common lab or manufacturing equipment. The mechanism may be implemented using simple circuits in a standard complementary metal oxide semiconductor process which requires very little area and can be powered off when it is not being used. The mechanism may include, for example, a low pass filter, a voltage divider for providing calibration reference voltage signals, a voltage to frequency converter, a frequency divider for dividing a frequency signal output so that the frequency of the signal is within a predetermined range, and an output driver and output pad. From the frequency output signal, a duty cycle of the signal under test may be calculated using off-chip equipment.
摘要翻译： 提供了一种用于测量诸如微处理器或片上系统的集成电路器件中被测信号占空比的机构。 该机制产生与占空比成比例的频率，可以使用普通实验室或制造设备测量。 该机构可以使用标准互补金属氧化物半导体工艺中的简单电路来实现，其需要非常小的面积并且可以在不使用时关闭电源。 该机构可以包括例如低通滤波器，用于提供校准参考电压信号的分压器，电压到频率转换器，用于分频频率信号输出的分频器，使得信号的频率在预定范围内 ，以及输出驱动器和输出板。 从频率输出信号，可以使用片外设备来计算被测信号的占空比。
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公开(公告)号：US20070255517A1
公开(公告)日：2007-11-01
申请号：US11380982
申请日：2006-05-01
申请人： David Boerstler , Eskinder Hailu , Jieming Qi
发明人： David Boerstler , Eskinder Hailu , Jieming Qi
IPC分类号： G06F19/00
CPC分类号： G01R31/31727 , G01R31/3004 , G01R31/31726
摘要： The disclosed methodology and apparatus measures the duty cycle of a reference clock signal that a clock circuit supplies to a duty cycle measurement (DCM) circuit located “on-chip”, namely on an integrated circuit (IC) in which the DCM circuit is incorporated. In one embodiment, the DCM circuit includes a capacitor driven by a charge pump. The reference clock signal drives the charge pump. The clock circuit varies the duty cycle of the reference clock signal among a number of known duty cycle values. The DCM circuit stores resultant capacitor voltage values corresponding to each of the known duty cycle values in a data store. The DCM circuit applies a test clock signal having an unknown duty cycle to the capacitor via the charge pump, thus charging the capacitor to a new voltage value that corresponds to the duty cycle of the test clock signal. Control software accesses the data store to determine the duty cycle to which the test clock signal corresponds.
摘要翻译： 所公开的方法和装置测量时钟电路提供给位于“片上”的占空比测量（DCM）电路的参考时钟信号的占空比，即集成电路（IC），其中并入DCM电路 。 在一个实施例中，DCM电路包括由电荷泵驱动的电容器。 参考时钟信号驱动电荷泵。 时钟电路在多个已知的占空比值之间改变参考时钟信号的占空比。 DCM电路将对应于每个已知占空比值的合成电容电压值存储在数据存储器中。 DCM电路通过电荷泵向电容器施加具有未知占空比的测试时钟信号，从而将电容器充电到对应于测试时钟信号占空比的新电压值。 控制软件访问数据存储，以确定测试时钟信号对应的占空比。
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公开(公告)号：US07260491B2
公开(公告)日：2007-08-21
申请号：US11260570
申请日：2005-10-27
申请人： David W. Boerstler , Eskinder Hailu , Jieming Qi
发明人： David W. Boerstler , Eskinder Hailu , Jieming Qi
IPC分类号： G06F19/00
CPC分类号： G01R29/02 , G01R31/2884
摘要： A mechanism for measuring duty cycle of a signal under test in an integrated circuit device, such as a microprocessor or system-on-a-chip is provided. The mechanism generates a frequency which is proportional to the duty cycle and which can be measured using common lab or manufacturing equipment. The mechanism may be implemented using simple circuits in a standard complementary metal oxide semiconductor process which requires very little area and can be powered off when it is not being used. The mechanism may include, for example, a low pass filter, a voltage divider for providing calibration reference voltage signals, a voltage to frequency converter, a frequency divider for dividing a frequency signal output so that the frequency of the signal is within a predetermined range, and an output driver and output pad. From the frequency output signal, a duty cycle of the signal under test may be calculated using off-chip equipment.
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94.发明申请APPARATUS AND METHOD FOR PROVIDING A REPROGRAMMABLE ELECTRICALLY PROGRAMMABLE FUSE 有权提供可编程可编程保险丝的装置和方法公开(公告)号：US20070081406A1
公开(公告)日：2007-04-12
申请号：US11246586
申请日：2005-10-07
申请人： David Boerstler , Eskinder Hailu , Subramanian Iyer , Jieming Qi
发明人： David Boerstler , Eskinder Hailu , Subramanian Iyer , Jieming Qi
IPC分类号： G11C17/18
摘要： An apparatus and method for providing a reprogrammable electrically programmable fuse (eFuse) are provided. With the apparatus and method, a pair of eFuses are provided coupled to programming current sources and sensing current sources. When the pair of eFuses is to be programmed, a first programming current is applied to a first eFuse to thereby increase the resistance of the first eFuse by an incremental amount. When the pair of eFuses is to be returned to an unprogrammed state, a second programming current source is applied to a second eFuse to thereby increase a resistance of the second eFuse to be greater than the resistance of the first eFuse. When the sensing current is applied to the eFuses, a difference in the resulting voltages across the eFuses is identified and used to indicate whether the reprogrammable eFuse is in a programmed state or unprogrammed state.
摘要翻译： 提供了一种用于提供可再编程电可编程熔丝（eFuse）的设备和方法。 利用该装置和方法，提供一对耦合到编程电流源并感测电流源的eFuses。 当要对一对eFuse进行编程时，将第一编程电流施加到第一eFuse，从而增加第一eFuse的电阻增量。 当一对eFuse将返回到未编程状态时，第二编程电流源被施加到第二eFuse，从而将第二eFuse的电阻增加到大于第一eFuse的电阻。 当感应电流被施加到eFuse时，识别出eFuses上产生的电压的差异，并用于指示可重新编程的eFuse是否处于编程状态或未编程状态。
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公开(公告)号：US20070057697A1
公开(公告)日：2007-03-15
申请号：US11227026
申请日：2005-09-15
申请人： David Boerstler , Eskinder Hailu , Jieming Qi
发明人： David Boerstler , Eskinder Hailu , Jieming Qi
IPC分类号： G01R29/02
CPC分类号： G01R31/31708 , G01R31/31725
摘要： An apparatus and method for verifying glitch-free operation of a multiplexer are provided. The apparatus includes a circuit having a plurality of flip-flop elements that receive as inputs the plurality of clock signals that are inputs to the multiplexer, and a corresponding synchronized output signal of a decoder generated based on control inputs to the decoder. The synchronized output signals from the decoder are used as trigger signals to the plurality of flip-flops. The flip-flops sample the clock signals based upon the trigger signals and provide outputs to a logic gate. The logic gate operates on the outputs from the flip-flops to generate an output signal indicative of whether glitch-free operation is verified or is not verified.
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96.发明申请Circuit to Reduce Transient Current Swings During Mode Transitions of High Frequency/High Power Chips 有权在高频/高功率芯片模式转换期间减少瞬态电流摆幅的电路公开(公告)号：US20080272820A1
公开(公告)日：2008-11-06
申请号：US12132871
申请日：2008-06-04
IPC分类号： H03K3/00
CPC分类号： H03K23/662 , G06F1/3203 , G06F1/324 , Y02D10/126
摘要： A method, an apparatus, and a computer program are provided to reduce transient current swings during mode transitions. Traditionally, transient supply voltage fluctuations on a chip account for a large portion of the power supply. The number of series inductances and resistances are typically minimized, while adding large decoupling capacitances between the supply voltage and ground. However, situations may arise where reduction of series inductances and resistances cannot be accomplished. Therefore, to assist in controlling the transient current swings, reduction of clocking frequencies are performed in a controlled manner.
摘要翻译： 提供了一种方法，装置和计算机程序以减少模式转换期间的瞬态电流摆动。 传统上，芯片上的瞬态电源电压波动占大部分电源。 串联电感和电阻的数量通常最小化，同时在电源电压和地之间增加大的去耦电容。 然而，不能实现串联电感和电阻的降低的情况。 因此，为了帮助控制瞬态电流摆动，以受控的方式执行时钟频率的降低。
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97.发明授权Circuit to reduce transient current swings during mode transitions of high frequency/high power chips 有权在高频/高功率芯片的模式转换期间减少瞬态电流摆幅的电路公开(公告)号：US07831006B2
公开(公告)日：2010-11-09
申请号：US12132871
申请日：2008-06-04
CPC分类号： H03K23/662 , G06F1/3203 , G06F1/324 , Y02D10/126
摘要： An apparatus is provided to reduce transient current swings during mode transitions. Traditionally, transient supply voltage fluctuations on a chip account for a large portion of the power supply. The number of series inductances and resistances are typically minimized, while adding large decoupling capacitances between the supply voltage and ground. However, situations may arise where reduction of series inductances and resistances cannot be accomplished. Therefore, to assist in controlling the transient current swings, reduction of clocking frequencies are performed in a controlled manner.
摘要翻译： 提供了一种用于减少模式转换期间的瞬态电流摆动的装置。 传统上，芯片上的瞬态电源电压波动占大部分电源。 串联电感和电阻的数量通常最小化，同时在电源电压和地之间增加大的去耦电容。 然而，不能实现串联电感和电阻的降低的情况。 因此，为了帮助控制瞬态电流摆动，以受控的方式执行时钟频率的降低。
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公开(公告)号：US07242233B2
公开(公告)日：2007-07-10
申请号：US10692416
申请日：2003-10-23
IPC分类号： H03K3/017
CPC分类号： G06F1/04 , H03K5/04 , H03K5/1565
摘要： The present invention provides for correcting excessive pulse widths using incremental delays. The pulse width is evaluated through a correction block and leak detector. An acceptable pulse passes through an interconnect directly to the clock output. Unacceptable pulses are sent through a block delay module that incorporates a series of delay sub-blocks that disconnect and reset in accordance with a pre-programmed total delay time. The conditioned clock pulse is resent through a node to the correction block and leak detector where it is reevaluated. If the pulse is acceptable, it is sent to the clock output. If the pulse is found unacceptable, it is recycled again. A high low clock pulse shuttle determines and alters the high or low state of the clock pulse to ensure a correct output to downstream dependent devices.
摘要翻译： 本发明提供使用增量延迟来校正过多的脉冲宽度。 通过校正块和泄漏检测器来评估脉冲宽度。 可接受的脉冲通过互连直接连接到时钟输出。 不可接受的脉冲通过块延迟模块发送，该模块延迟模块包含一系列根据预编程的总延迟时间断开和复位的延迟子块。 经调节的时钟脉冲通过节点重新发送到校正块和泄漏检测器，在那里它被重新评估。 如果脉冲是可接受的，则将其发送到时钟输出。 如果发现脉冲不可接受，则再次被再循环。 高时钟脉冲穿梭确定并改变时钟脉冲的高或低状态，以确保向下游相关设备输出正确的输出。
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公开(公告)号：US07890561B2
公开(公告)日：2011-02-15
申请号：US11204402
申请日：2005-08-16
CPC分类号： G06F7/588 , H04L9/001 , H04L9/0869
摘要： A random number generator, a method, and a computer program product are provided for producing a random number seed. Each oscillator within an array of oscillators operates at a different frequency. The operating frequencies of each oscillator are not harmonically related, such that no integer multiple exists between the frequencies of any two oscillators. In one embodiment, the outputs of the array of oscillators connect to a multiple input latch. The multiple input latch also receives a sample signal, which is a clock signal. The clock signal samples the outputs of the array of oscillators, and the multiple input latch in conjunction with the random number determination logic (“RNDL”) produces a digital output (0 or 1) for each oscillator within the array. The RNDL uses these digital outputs to create a random number seed.
摘要翻译： 提供随机数生成器，方法和计算机程序产品用于产生随机数种子。 振荡器阵列内的每个振荡器以不同的频率工作。 每个振荡器的工作频率不是谐波相关的，使得在任何两个振荡器的频率之间不存在整数倍。 在一个实施例中，振荡器阵列的输出连接到多输入锁存器。 多输入锁存器还接收作为时钟信号的采样信号。 时钟信号对振荡器阵列的输出采样，并且多输入锁存器与随机数确定逻辑（“RNDL”）一起为阵列内的每个振荡器产生数字输出（0或1）。 RNDL使用这些数字输出创建一个随机数字种子。
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100.发明授权Circuit to reduce power supply fluctuations in high frequency/high power circuits 有权降低高频/高功率电路电源波动的电路公开(公告)号：US07809974B2
公开(公告)日：2010-10-05
申请号：US12014830
申请日：2008-01-16
IPC分类号： H04L25/00
CPC分类号： G06F1/26
摘要： A circuit for transitioning clocking speeds, or frequencies, is provided. With this circuit, a clocking circuit providing a first clock signal at a first clock frequency is coupled to a counter. A comparator and a first divider are coupled to an output of the counter. The first divider outputs a second clock signal at a second clock frequency. A second divider is interposed between the clocking circuit and the counter. A processor is coupled to an output of the first divider.
摘要翻译： 提供了用于转换时钟速度或频率的电路。 利用该电路，以第一时钟频率提供第一时钟信号的时钟电路被耦合到计数器。 比较器和第一分频器耦合到计数器的输出端。 第一分频器以第二时钟频率输出第二时钟信号。 在时钟电路和计数器之间插入第二分频器。 处理器耦合到第一分频器的输出端。
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