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公开(公告)号：US07119920B2
公开(公告)日：2006-10-10
申请号：US10924894
申请日：2004-08-25
申请人： Hiroyuki Takahashi
发明人： Hiroyuki Takahashi
IPC分类号： B41L3/14
CPC分类号： B41J3/546 , B41J13/106 , G06K15/02 , G06K2215/0088 , G06K2215/0094
摘要： In case of forming images of a job, which includes color pages and black/white pages, in order to constitute a system which can obtain pages of individually formed images with a state in original page order by selectively using both a color image formation apparatus and a monochrome image formation apparatus with a simple operation, job contents are transferred to each of the color image formation apparatus and the monochrome image formation apparatus when the job, which includes the color pages and the black/white pages, is outputted from a computer. The color image formation apparatus forms only images of color pages, and then an user sets the color pages in an inserter. The monochrome image formation apparatus forms monochrome images when pages are black/white and feeds sheets from the inserter when pages are color.
摘要翻译： 在形成包括彩色页和黑/白页的作业的图像的情况下，为了构成可以通过选择性地使用彩色图像形成装置和/或图像形成装置来获得具有原始页面顺序的状态的单独形成的图像的页面的系统 当从计算机输出包括彩色页面和黑白页面的作业时，具有简单操作的单色图像形成装置将作业内容传送到彩色图像形成装置和单色图像形成装置中的每一个。 彩色图像形成装置仅形成彩色图像，然后用户将彩色页面设置在插入器中。 当页面是黑色/白色时，单色图像形成装置形成单色图像，并且当页面是彩色时从插入器馈送纸张。
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公开(公告)号：US20060198226A1
公开(公告)日：2006-09-07
申请号：US11360593
申请日：2006-02-24
申请人： Hiroyuki Takahashi , Takuya Hirota
发明人： Hiroyuki Takahashi , Takuya Hirota
IPC分类号： G11C7/00
CPC分类号： G11C11/40615 , G11C11/406 , G11C2211/4061 , G11C2211/4067
摘要： A semiconductor storage device according to an embodiment of the present invention includes: a plurality of word lines; a plurality of memory cells corresponding to the plurality of word lines; and a refresh circuit for sequentially driving the plurality of word lines to refresh each of the plurality of memory cells based on a timer period, which sets the timer period in accordance with a disturb amount in an active mode upon shift from the active mode to the standby mode.
摘要翻译： 根据本发明实施例的半导体存储装置包括：多个字线; 与所述多个字线对应的多个存储单元; 以及刷新电路，用于根据定时器周期顺序驱动多个字线以刷新每个多个存储单元，该定时器周期根据从活动模式转换到活动模式时的活动模式中的干扰量来设置定时器周期 待机模式。
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公开(公告)号：US20060175387A1
公开(公告)日：2006-08-10
申请号：US10546871
申请日：2004-02-24
申请人： Tohru Yukumoto , Hiroyuki Takahashi
发明人： Tohru Yukumoto , Hiroyuki Takahashi
CPC分类号： B65D77/2032 , B65D1/28
摘要： An easy-open packaging body 1 includes: a container body 10 with a flange 14 formed on a circumference of an opening 13, and a cover 20 heat-sealed to the flange 14 to close the opening 13. Inner and outer notches 15A and 15B enclosing the opening 13 are formed respectively on inner and outer circumferential sides on the flange 14. The flange 14 and the cover 20 are heat-sealed by a first seal part 16A having a predetermined width and formed between the inner and outer notches 15A and 15B to enclose the opening 13 and a second seal part 16B having a width narrower than that of the first seal part 16A and formed within an area of the first seal part 16A to enclose the opening 13 along the first seal part 16A, the second seal part 16B having a projected seal part 17 projected outward relative to the other part on a position corresponding to a tab 21.
摘要翻译： 容易开封的包装体1包括：容器主体10，其具有形成在开口13的圆周上的凸缘14;以及盖20，其被热密封到凸缘14以封闭开口13。 分别在凸缘14的内周侧和外周侧形成封闭开口13的内切口15和外切口15B。 凸缘14和盖20由具有预定宽度的第一密封部分16A热封，形成在内切口15A和外切口15B之间以封闭开口13，第二密封部分16B具有宽度 比第一密封部分16A的狭窄，并且形成在第一密封部分16A的区域内，沿着第一密封部分16A围绕开口13，第二密封部分16B具有向外突出的突出的密封部分17 到对应于翼片21的位置的另一部分。
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94.发明授权Semiconductor memory device for preventing a late write from disturbing a refresh operation 有权半导体存储装置，用于防止后期写入干扰刷新操作公开(公告)号：US07089351B2
公开(公告)日：2006-08-08
申请号：US10479635
申请日：2002-05-28
IPC分类号： G06F12/16
CPC分类号： G11C11/40603 , G11C11/406 , G11C11/40615 , G11C2211/4067
摘要： A semiconductor memory device is provided for preventing a late-write from disturbing a refresh operation and also for reducing a current consumption in a write cycle with execution of the late-write. Upon a transition of an address ADD, an address transition detector circuit detects this address transition. Upon receipt of a result of detection by the address transition detector circuit, a state control circuit judges an operation to be executed, from an output enable signal /OE and a write enable signal /WE, and then outputs any of a read statement RS, a write statement WS, and a refresh statement FS. According to a clock signal ACLK, input signals such as addresses are taken for executions of operations based on the statements.
摘要翻译： 提供一种半导体存储器件，用于防止后期写入干扰刷新操作，并且还用于通过执行后期写入来减少写周期中的电流消耗。 地址转换检测器电路在地址ADD的转换时检测该地址转换。 一旦状态控制电路接收到由地址转换检测器电路检测到的结果，就从输出使能信号/ OE和写使能信号/ WE判断要执行的操作，然后输出读出的语句RS， 写入语句WS和刷新语句FS。 根据时钟信号ACLK，基于语句执行诸如地址的输入信号来执行操作。
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公开(公告)号：US20060165423A1
公开(公告)日：2006-07-27
申请号：US11330181
申请日：2006-01-12
IPC分类号： G03G15/08
CPC分类号： G03G15/0121 , G03G2215/0119
摘要： The image forming apparatus includes first and second developing apparatuses for developing electrostatic images on first and second image bearing members, a first developer container containing a developer, first supplying means for supplying the developer in the first developer container to the first developing apparatus, a second developer container containing a developer to be supplied to the second developing apparatus, second supplying means for supplying the developer in the second developer container to the second developing apparatus, driving means for driving the first and second supplying means, changeover means which changes over the driving force of the driving means during one image forming operation to first and second states in which the driving force is respectively transmitted to each of the first and second supplying means, and control means for changing the times of the first and second states according to a condition of an image to be formed.
摘要翻译： 图像形成装置包括用于在第一和第二图像承载部件上显影静电图像的第一和第二显影装置，容纳显影剂的第一显影剂容器，用于将第一显影剂容器中的显影剂供应到第一显影装置的第一供给装置， 含有供给第二显影装置的显影剂的显影剂容器，用于将第二显影剂容器中的显影剂供应到第二显影装置的第二供给装置，用于驱动第一和第二供给装置的驱动装置，切换驱动装置 在一个图像形成操作期间驱动装置的力分别传递到第一和第二供给装置中的每一个的第一和第二状态，以及根据条件改变第一和第二状态的时间的控制装置 要形成的图像。
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公开(公告)号：US20060114735A1
公开(公告)日：2006-06-01
申请号：US11273014
申请日：2005-11-15
申请人： Hiroyuki Takahashi
发明人： Hiroyuki Takahashi
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C11/40615 , G11C2211/4061
摘要： Disclosed is a semiconductor-memory device comprising a selector for performing switching control such that in the standby state the refresh operation is performed responsive to an external-refresh-execution command supplied from outside the semiconductor-memory device, while in the active state, the refresh operation is performed, not under the control from outside the semiconductor-memory device, but under the control from a built-in timer.
摘要翻译： 公开了一种半导体存储器件，包括：选择器，用于执行切换控制，使得在待机状态下，响应于从半导体存储器件外部提供的外部刷新执行命令执行刷新操作，而在激活状态下， 执行刷新操作，而不是在半导体存储器件外部的控制下，而是在内置定时器的控制下进行。
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公开(公告)号：US07054223B2
公开(公告)日：2006-05-30
申请号：US10920249
申请日：2004-08-18
申请人： Hiroyuki Takahashi , Takuya Hirota
发明人： Hiroyuki Takahashi , Takuya Hirota
IPC分类号： G11C8/00
CPC分类号： G11C11/40603 , G11C8/18 , G11C11/406
摘要： A semiconductor memory device adapted for avoiding collision between the selection period of a word line for a refresh and the selection period of a word line for a read/write, comprises a cell array including a plurality of memory cells that require refreshing for retention of storage data and means for exercising control so that when a read/write request is input in a clock cycle following a clock cycle for performing a refresh operation, a read/write operation in the cell array is delayed by at least one clock cycle, and the read/write operation is started after completion of the refresh.
摘要翻译： 适于避免用于刷新的字线的选择周期与用于读/写的字线的选择周期之间的冲突的半导体存储器件包括包括需要刷新以保持存储的多个存储器单元的单元阵列 用于执行控制的数据和装置，使得当在执行刷新操作的时钟周期之后的时钟周期中输入读/写请求时，单元阵列中的读/写操作被延迟至少一个时钟周期，并且 读/写操作在完成刷新后开始。
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公开(公告)号：US07029833B2
公开(公告)日：2006-04-18
申请号：US10364494
申请日：2003-02-11
IPC分类号： G03F1/73
CPC分类号： C09K11/06 , C09K2211/1011 , C09K2211/1014 , C09K2211/1029 , G03C1/73 , H05B33/14 , Y10S430/163
摘要： An image display medium that includes a photoconductive layer containing a photochromic compound and an electron accepting compound; and a substrate, in which the photochromic compound contains a fulgide compound, and the electron accepting compound contains a compound selected at least from: a) a phosphonic acid compound having an aliphatic group containing 12 or more carbon atoms; b) an aliphatic carboxylic acid compound having an aliphatic group containing 12 or more carbon atoms; and c) a phenolic compound having an aliphatic group containing 12 or more carbon atoms, a process for forming an image using the medium, and a multicolor image-forming apparatus using the medium and suitable for the process.
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公开(公告)号：US07023771B2
公开(公告)日：2006-04-04
申请号：US10911634
申请日：2004-08-05
IPC分类号： G11B5/09
CPC分类号： G11B33/1406 , G11B7/1263
摘要： An optical information recording apparatus includes an emission output information acquisition section for acquiring information about a drive current employed for controlling a beam output from an information recording section; a cooling determination section for determining whether to cool the information recording section in accordance with the information about the emission output acquired by the emission output information acquisition section; and a cooling execution section for cooling the information recording section when the cooling determination section has determined that cooling should be performed.
摘要翻译： 光信息记录装置包括发射输出信息获取部分，用于获取关于用于控制从信息记录部分输出的光束的驱动电流的信息; 冷却判定部分，用于根据关于由排放输出信息获取部分获取的排放输出的信息来确定是否冷却信息记录部分; 以及冷却执行部，其在所述冷却判定部判定为要进行冷却时，冷却所述信息记录部。
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100.发明申请Internal voltage level control circuit and semiconductor memory device as well as method of controlling the same 有权内部电压电平控制电路和半导体存储器件以及其控制方法公开(公告)号：US20060044889A1
公开(公告)日：2006-03-02
申请号：US11202880
申请日：2005-08-12
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C5/145 , G11C5/147 , G11C8/08 , G11C11/40615 , G11C11/4074 , G11C11/4085 , G11C2211/4068
摘要： There are provided a voltage level control circuit with a reduced power consumption and a method of controlling the same. When a signal “A” is in a “L” level and a signal PL entered from the outside of the voltage level control circuit becomes “H” level, a latch signal La outputted from a latch (11) becomes “H” level, whereby NFETs (14, 17, 24) turn ON. A voltage dividing circuit comprising resistances (12, 13) and current mirror differential amplifiers (20, 27) are placed in active states to output “H” as a signal A which controls a boost voltage Vbt (word line driving voltage. As the boost voltage Vbt is increased and reaches to a reference voltage Vref2, a voltage V2 becomes “H”, whereby the signal A becomes “L”. After the signal A become “L”, the latch (11) is made through. At this time, the signal PL is “L”, the latch signal La outputted from the latch (11) becomes “L”, whereby the NFETs (14, 7, 24) turn OFF. As described here, the NFETs (14, 7, 24) is kept OFF in the other time period than when needed, in order to reduce the power consumption.
摘要翻译： 提供了具有降低的功耗的电压电平控制电路及其控制方法。 当信号“A”处于“L”电平并且从电压电平控制电路的外部输入的信号PL变为“H”电平时，从锁存器（11）输出的锁存信号La变为“H”电平， 由此NFET（14,17,24）导通。 包括电阻（12,13）和电流镜差分放大器（20,27）的分压电路被置于有效状态，以输出“H”作为控制升压电压Vbt（字线驱动电压）的信号A，作为升压 电压Vbt增加并达到参考电压Vref 2，电压V 2变为“H”，由此信号A变为“L”，在信号A变为“L”之后，锁存器（11）通过 这时，信号PL为“L”，从闩锁（11）输出的锁存信号La变为“L”，由此NFET（14,7,24）截止，如上所述，NFET（14,7 ，24）在需要时的其他时间段内保持OFF，以便降低功耗。
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