公开(公告)号：US07746711B2

公开(公告)日：2010-06-29

申请号：US11984606

申请日：2007-11-20

申请人： Hideo Inaba

发明人： Hideo Inaba

IPC分类号： G11C7/00

CPC分类号： G11C7/1027 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/22 ,  G11C11/4076

摘要： High-speed operation is achieved without increase in a circuit current and unstable operation of data strobe signal level due to collision between data strobe signals. Each of RAMs 11a and 11b outputs a data signal DQ and a data strobe signal DQS indicative of an output timing of the data signal. RAM 11a includes a strobe signal control unit 15a that determines whether RAM 11b connected in parallel with the RAM 11a is in a read state or not, and delays an output start timing of data strobe signal DQS when the RAM 11b is in the read state. Strobe signal control unit 15a of the RAM 11a controls output start timing so that a latter half portion of a preamble period of the data strobe signal DQS to be output coincides with a postamble period of the data strobe signal DQS output by the RAM 11b.

摘要翻译： 由于数据选通信号之间的冲突，电路电流不增加，数据选通信号电平不稳定，实现高速运行。 每个RAM11a和11b输出数据信号DQ和表示数据信号的输出定时的数据选通信号DQS。 RAM 11a包括选通信号控制单元15a，其确定与RAM 11a并联连接的RAM 11b是否处于读取状态，并且当RAM 11b处于读取状态时延迟数据选通信号DQS的输出开始定时。 RAM 11a的选通信号控制单元15a控制输出开始定时，使得要输出的数据选通信号DQS的前导码周期的后半部分与RAM 11b输出的数据选通信号DQS的后同步周期一致。

公开(公告)号：US20090316495A1

公开(公告)日：2009-12-24

申请号：US12488920

申请日：2009-06-22

申请人： Hideo INABA ,  Tadashi ONODERA

发明人： Hideo INABA ,  Tadashi ONODERA

IPC分类号： G11C7/10 ,  G11C29/00 ,  G11C8/18

CPC分类号： G11C29/48 ,  G11C29/1201

摘要： A semiconductor device includes: first and second input/output terminals; a first input/output line connected to the first input/output terminal; a second input/output line connected to the second input/output terminal; and a first by-path route that connects the first input/output line and the second input/output line. When in normal operation mode, the first by-path route is set in a non-conductive state. When in a test mode, the first by-path route is set into a conductive state so that a first data inputted to the first input/output terminal is outputted as a first data to the second input/output line, in correspondence with a transition of a clock signal in the first direction, and so that a second data inputted to said first input/output terminal is outputted as a second input data for said first input/output line, in correspondence with a transition of said clock signal in the second direction.

摘要翻译： 半导体器件包括：第一和第二输入/输出端子; 连接到第一输入/输出端的第一输入/输出线; 连接到第二输入/输出端子的第二输入/输出线; 以及连接第一输入/输出线和第二输入/输出线的第一旁路路径。 当处于正常操作模式时，第一个旁路路由被设置为非导通状态。 当处于测试模式时，将第一旁路路径设置为导通状态，使得输入到第一输入/输出端的第一数据作为第一数据输出到第二输入/输出线， 并且使得输入到所述第一输入/输出端的第二数据作为所述第一输入/输出线的第二输入数据被输出，以对应于所述第二输入/输出端中的所述时钟信号的转变 方向。

公开(公告)号：US20060245098A1

公开(公告)日：2006-11-02

申请号：US11411152

申请日：2006-04-26

申请人： Yasuyoshi Suzuki ,  Hideo Inaba ,  Jouji Yamaguchi ,  Toshiki Fujiyoshi ,  Akira Tsunoda

发明人： Yasuyoshi Suzuki ,  Hideo Inaba ,  Jouji Yamaguchi ,  Toshiki Fujiyoshi ,  Akira Tsunoda

IPC分类号： G11B5/00

CPC分类号： F01L13/0015 ,  F01L1/185 ,  F01L1/2405 ,  F01L2820/032

摘要： A feed screw mechanism including a screwed shaft which moves linearly along with the control shaft, and a rotation spindle which rotates in a circumferential direction. The feed screw mechanism converts a rotational movement of the rotation spindle into a linear movement of the screwed shaft. A protrusion protrudes outwardly from the rotation spindle. An internal thread member engages with an outer wall surface of the rotation spindle. A motor stator generating a magnetic is positioned over the rotation spindle, and is sandwiched between the protrusion and the internal thread member in an axial direction of the rotation spindle.

公开(公告)号：US07100553B2

公开(公告)日：2006-09-05

申请号：US11156487

申请日：2005-06-21

申请人： Yasuyoshi Suzuki ,  Akihiko Kameshima ,  Hideo Inaba ,  Jouji Yamaguchi

发明人： Yasuyoshi Suzuki ,  Akihiko Kameshima ,  Hideo Inaba ,  Jouji Yamaguchi

IPC分类号： F01L1/34

CPC分类号： F01L13/0063 ,  F01L1/044 ,  F01L1/08 ,  F01L1/185 ,  F01L1/2405 ,  F01L1/267 ,  F01L2105/00 ,  F01L2820/032 ,  F02D13/0207 ,  Y02T10/18 ,  Y10T74/2107

摘要： An actuator for a valve lift control device linearly moves a control shaft to change a valve lift in accordance with an axial position of the control shaft. A first and a second rotation cam integrally rotate around a common rotation axis by transmission of torque, so that a direct acting follower, which includes a first and a contact members, linearly moves with a control shaft. The first and a second rotation cams are respectively in contact with the first and the second contact members via a first and a second contact points. The first contact point is located on the opposite side of the second contact point with respect to the rotation axis. A sum of a first rotation cam lift of the first rotation cam and a second rotation cam lift of the second rotation cam is substantially constant in a predetermined rotation angular range of the first rotation cam and the second rotation cam.

摘要翻译： 用于气门升程控制装置的致动器根据控制轴的轴向位置线性移动控制轴以改变气门升程。 第一旋转凸轮和第二旋转凸轮通过扭矩的传递一体地围绕公共旋转轴旋转，使得包括第一和接触部件的直动随动件与控制轴线性地移动。 第一和第二旋转凸轮分别经由第一和第二接触点与第一和第二接触构件接触。 第一接触点相对于旋转轴线位于第二接触点的相反侧。 第一旋转凸轮的第一旋转凸轮升程和第二旋转凸轮的第二旋转凸轮升程的总和在第一旋转凸轮和第二旋转凸轮的预定旋转角度范围内基本上恒定。

公开(公告)号：US07089351B2

公开(公告)日：2006-08-08

申请号：US10479635

申请日：2002-05-28

申请人： Hiroyuki Takahashi ,  Atsushi Nakagawa ,  Hideo Inaba

发明人： Hiroyuki Takahashi ,  Atsushi Nakagawa ,  Hideo Inaba

IPC分类号： G06F12/16

CPC分类号： G11C11/40603 ,  G11C11/406 ,  G11C11/40615 ,  G11C2211/4067

摘要： A semiconductor memory device is provided for preventing a late-write from disturbing a refresh operation and also for reducing a current consumption in a write cycle with execution of the late-write. Upon a transition of an address ADD, an address transition detector circuit detects this address transition. Upon receipt of a result of detection by the address transition detector circuit, a state control circuit judges an operation to be executed, from an output enable signal /OE and a write enable signal /WE, and then outputs any of a read statement RS, a write statement WS, and a refresh statement FS. According to a clock signal ACLK, input signals such as addresses are taken for executions of operations based on the statements.

摘要翻译： 提供一种半导体存储器件，用于防止后期写入干扰刷新操作，并且还用于通过执行后期写入来减少写周期中的电流消耗。 地址转换检测器电路在地址ADD的转换时检测该地址转换。 一旦状态控制电路接收到由地址转换检测器电路检测到的结果，就从输出使能信号/ OE和写使能信号/ WE判断要执行的操作，然后输出读出的语句RS， 写入语句WS和刷新语句FS。 根据时钟信号ACLK，基于语句执行诸如地址的输入信号来执行操作。

公开(公告)号：US20050047239A1

公开(公告)日：2005-03-03

申请号：US10500400

申请日：2002-12-25

申请人： Hiroyuki Takahashi ,  Takuya Hirota ,  Noriaki Komatsu ,  Atsushi Nakagawa ,  Susumu Takano ,  Masahiro Yoshida ,  Yuuji Torige ,  Hideo Inaba

发明人： Hiroyuki Takahashi ,  Takuya Hirota ,  Noriaki Komatsu ,  Atsushi Nakagawa ,  Susumu Takano ,  Masahiro Yoshida ,  Yuuji Torige ,  Hideo Inaba

IPC分类号： G11C11/403 ,  G11C11/406 ,  G11C7/00

CPC分类号： G11C11/40603 ,  G11C11/406

摘要： Refresh of memory cells is performed periodically by a refresh timer, and collision between memory access and memory refresh is avoided. When memory access occurs, an F/F 163 is set by a one shot pulse from an OS circuit 161, a memory access request is inputted to a memory accessing pulse generator circuit 171 through a NOR gate 167, and a latch control signal LC and an enable signal REN are outputted. When a refresh request from the refresh timer is inputted to an AND gate 168 during the memory access, the output of the NOR gate 167 is at the “L” level, and the refresh request is blocked by the AND gate 168. Thereafter, at the time when the latch control signal LC is turned into the “L” level, F/Fs 163, 164 and 165 are reset, the output of the NOR gate 167 is turned into the “H” level, the refresh request is inputted to a refreshing pulse generator circuit 170, and a refresh enable signal RERF is outputted.

摘要翻译： 通过刷新定时器周期性地执行存储器单元的刷新，并避免存储器访问和存储器刷新之间的冲突。 当存储器访问发生时，通过来自OS电路161的单触发脉冲设置F / F 163，通过NOR门167将存储器访问请求输入到存储器访问脉冲发生器电路171，以及锁存控制信号LC和 输出使能信号REN。 当在存储器访问期间来自刷新定时器的刷新请求被输入到与门168时，或非门167的输出处于“L”电平，刷新请求由与门168阻止。此后， 当锁存控制信号LC变为“L”电平时，F / F 163,164和165被复位，或非门167的输出变成“H”电平，刷新请求被输入到 输出刷新脉冲发生器电路170和刷新使能信号RERF。

公开(公告)号：US06646956B2

公开(公告)日：2003-11-11

申请号：US10221249

申请日：2002-09-10

申请人： Hiroyuki Takahashi ,  Hideo Inaba ,  Masatoshi Sonoda

发明人： Hiroyuki Takahashi ,  Hideo Inaba ,  Masatoshi Sonoda

IPC分类号： G11C800

CPC分类号： H03K5/1534 ,  G11C8/18 ,  H03K2005/00293

摘要： A one-shot signal generation circuit is provided which makes it easy to adjust pulse width and to deal with variation of skew of an ATD signal, and can reduce chip area. A timing determination section (100) is reset by an edge of a first detected signal among a plurality of address transition detection signals (ATD signals) which have arrived within the skew period of an address signal, measures a first predetermined time by taking an edge of a second detected signal as start instant, and outputs a signal DST which reflects the result of this measurement. A timing determination section (110) measures a second predetermined time by taking an edge of the first detected signal as start instant, and outputs a signal PG which reflects the result of this measurement. An LC generation circuit (14) outputs a one-shot signal (LC) whose start instant is determined by the signal PG and whose end instant is determined by the signal DST.

摘要翻译： 提供了一个单触发信号发生电路，可以方便的调整脉冲宽度并应对ATD信号的偏斜变化，并可以减少芯片面积。 定时确定部分（100）由在地址信号的歪斜时段内到达的多个地址转换检测信号（ATD信号）中的第一检测信号的边沿复位，通过取边缘来测量第一预定时间 的第二检测信号作为开始时刻，并且输出反映该测量结果的信号DST。 定时确定部分（110）通过将第一检测信号的边缘作为开始时刻来测量第二预定时间，并且输出反映该测量结果的信号PG。 LC生成电​​路（14）输出由信号PG确定开始时刻的单触发信号（LC），并且由信号DST确定其结束时刻。

公开(公告)号：US5351670A

公开(公告)日：1994-10-04

申请号：US976940

申请日：1992-11-18

申请人： Kaneo Buma ,  Katsumaru Oda ,  Hideo Inaba

发明人： Kaneo Buma ,  Katsumaru Oda ,  Hideo Inaba

IPC分类号： F02P7/02 ,  H01R39/60 ,  F02P1/00

CPC分类号： F02P7/026 ,  F02P7/022 ,  H01R39/60

摘要： An ignition distributor has a hollow housing. A distributor cap having a caved portion that extends in the housing is mounted on one end of the housing. The other end of the housing supports a rotation shaft. An ignition coil is disposed in the caved portion of the distributor cap. A rotor electrode of a distributor section is connected to the shaft, and rotates around the caved portion of the distributor cap. Side electrodes are arranged to face the rotor electrode with its rotation. Thus, the space surrounding the ignition coil is fully utilized to arrange the distributor section. This results in a compact ignition distributor.

摘要翻译： 点火分配器具有中空壳体。 具有在壳体中延伸的凹陷部分的分配器盖安装在壳体的一端。 壳体的另一端支撑旋转轴。 点火线圈设置在分配器盖的凹陷部分中。 分配器部分的转子电极连接到轴，并且围绕分配器盖的凹陷部分旋转。 侧电极被设置成与其转动面对转子电极。 因此，充分利用围绕点火线圈的空间来布置分配器部分。 这导致紧凑的点火分配器。

公开(公告)号：US4812161A

公开(公告)日：1989-03-14

申请号：US760158

申请日：1985-07-29

申请人： Kenji Hagiwara ,  Hisao Ishikawa ,  Hideo Hosaka ,  Hideo Inaba

发明人： Kenji Hagiwara ,  Hisao Ishikawa ,  Hideo Hosaka ,  Hideo Inaba

IPC分类号： A01N43/90 ,  A01N55/10 ,  A01P13/00 ,  C07D513/04 ,  A01N43/82 ,  C07D251/24 ,  C07D285/14 ,  C07D401/04

CPC分类号： C07D513/04 ,  A01N43/90

摘要： Thia-diazole derivatives having the following partial structural formula had selective herbicidal activity on some crops. A process for producing these compounds is also disclosed: ##STR1##

摘要翻译： 具有以下部分结构式的噻二唑衍生物对一些作物具有选择性除草活性。 还公开了制备这些化合物的方法：

公开(公告)号：US07054224B2

公开(公告)日：2006-05-30

申请号：US10478369

申请日：2002-05-23

申请人： Hiroyuki Takahashi ,  Hideo Inaba ,  Atsushi Nakagawa

发明人： Hiroyuki Takahashi ,  Hideo Inaba ,  Atsushi Nakagawa

IPC分类号： G11C8/00

CPC分类号： G11C11/40615 ,  G11C7/1012 ,  G11C7/1051 ,  G11C11/406 ,  G11C11/4096

摘要： The present invention provides a non-synchronous semiconductor memory device configured as a pseudo-SRAM and capable of relaxing the limitation to address skew and improving the read rate. A data latch circuit 110 holds data having been read out of memory cells in a memory cell array 106 designated by a tow address included in an address ADD in a read mode. Upon transitions of column addresses A0, A1 included in the address, a multiplexer 111 sequentially and non-synchronously feeds out the data held in the data latch circuit 110 based on the column addresses A0, A1.

摘要翻译： 本发明提供一种被配置为伪SRAM的非同步半导体存储器件，并且能够放宽对寻址偏移的限制并提高读取速率。 数据锁存电路110将从存储单元读出的数据保存在由读取模式中包含在地址ADD中的拖尾地址指定的存储单元阵列106中。 在地址中包括的列地址A 0，A 1的转换中，多路复用器111基于列地址A 0，A 1顺序地并且不同步地馈送保存在数据锁存电路110中的数据。