公开(公告)号：US11263521B2

公开(公告)日：2022-03-01

申请号：US15251278

申请日：2016-08-30

Applicant: International Business Machines Corporation

Inventor： Tayfun Gokmen ,  Yurii A. Vlasov

IPC: G06N3/063 ,  G06N3/08

Abstract: A device, system, product and method of controlling resistive processing units (RPUs), includes applying an input voltage signal to each node of an array of resistive processing units, and controlling a learning rate of the array of resistive processing units by varying an amplitude of the input voltage signal to the array of resistive processing units. A conductance state of the array of resistive processing units is varied according to the amplitude received at each of the resistive processing units of the array of resistive processing units. The controlling of the amplitude of input voltage signal is according to a processor of a control device.

公开(公告)号：US11200297B2

公开(公告)日：2021-12-14

申请号：US16439246

申请日：2019-06-12

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Seyoung Kim ,  Tayfun Gokmen ,  Malte Rasch

IPC: G06N3/063 ,  H03F3/70 ,  G06F17/16 ,  G06N3/08

Abstract: An apparatus and method are provided for saturation prevention of a current integrator in a Resistive Processing Unit-based (RPU-based) accelerator. The apparatus includes a set of hardware switches. The apparatus further includes a voltage generator, operatively coupled between an input terminal and an output terminal of the current integrator, reducing a magnitude of an output voltage at the output terminal of the current integrator during a current integration operation by selectively applying a non-zero initial voltage to the current integrator prior to the current integration operation, responsive to an operating state of the set of hardware switches.

公开(公告)号：US11188826B2

公开(公告)日：2021-11-30

申请号：US16423398

申请日：2019-05-28

Applicant: International Business Machines Corporation

Inventor： Tayfun Gokmen ,  Seyoung Kim

IPC: G06N3/08 ,  G06N3/04 ,  G06N3/063 ,  G06N20/00

Abstract: In some aspects, a method may include initializing a first array and a second array with a random voltage value, passing a forward pass by pulsing an input voltage value from an input of the first array and an input of the second array, and reading output voltage values at an output of the first array and an output of the second array. The method may further include passing a backward pass into the inputs of both of the first and second arrays, and reading voltage values at the inputs of the first and second arrays. The method may further include updating, with the first array, a first matrix update on the first array, updating, with the second array, a first matrix update on the second, and updating, with the second array, a second matrix update on the second array.

公开(公告)号：US11157810B2

公开(公告)日：2021-10-26

申请号：US15954170

申请日：2018-04-16

Applicant: International Business Machines Corporation

Inventor： Seyoung Kim ,  Tayfun Gokmen

IPC: G06N3/08 ,  G06N3/04 ,  G06N3/063

Abstract: Systems and methods are provided to perform weight update operations in a resistive processing unit (RPU) system to update weight values of RPU devices comprising tunable resistive device. A weight update operation for a given RPU device includes maintaining a weight update accumulation value for the RPU device, adjusting the weight update accumulation value by one unit update value in response to a detected coincidence of stochastic bits streams of input vectors applied on an update row and update column control lines connected to the RPU device, generating a weight update control signal in response to the accumulated weight value reaching a predefined threshold value, and adjusting a conductance level of the tunable resistive device by one unit conductance value in response to the weight update control signal, wherein the one unit conductance value corresponds to one unit weight value of the RPU device.

公开(公告)号：US20210117373A1

公开(公告)日：2021-04-22

申请号：US17135335

申请日：2020-12-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Tayfun Gokmen

IPC: G06F15/80 ,  G06F15/78 ,  G06F9/38

Abstract: A processor includes an array of resistive processing units connected between row and column lines with a resistive element. A first single instruction, multiple data processing unit (SIMD) is connected to the row lines. A second SIMD is connected to the column lines. A first instruction issuer is connected to the first SIMD to issue instructions to the first SIMD, and a second instruction issuer is connected to the second SIMD to issue instructions to the second SIMD such that the processor is programmable and configurable for specific operations depending on an issued instruction set.

公开(公告)号：US10831860B2

公开(公告)日：2020-11-10

申请号：US16158056

申请日：2018-10-11

Applicant: International Business Machines Corporation

Inventor： Seyoung Kim ,  Hyungjun Kim ,  Tayfun Gokmen ,  Malte Rasch

IPC: G06F17/16

Abstract: Zero-shifting techniques in analog crosspoint arrays are provided. In one aspect, an analog array-based vector-matrix multiplication includes: a weight array connected to a reference array, each including a crossbar array having a set of conductive row wires and a set of conductive column wires intersecting the set of conductive row wires, and optimizable crosspoint devices at intersections of the set of conductive column wires and the set of conductive row wires. A method for analog array-based vector-matrix computing is also provided that includes: applying repeated voltage pulses to the crosspoint devices in the weight array until all of the crosspoint devices in the weight array converge to their own symmetry point; and copying conductance values for each crosspoint device from the weight array to the reference array.

公开(公告)号：US20200349440A1

公开(公告)日：2020-11-05

申请号：US16400674

申请日：2019-05-01

Applicant: International Business Machines Corporation

Inventor： Tayfun Gokmen

IPC: G06N3/08 ,  G06N3/04 ,  G06N3/063 ,  G06N20/10

Abstract: In one aspect, a method of training a DNN includes: providing a weight matrix (W) as a linear combination of matrices/arrays A and C; in a forward cycle, transmitting an input vector x through arrays A and C and reading output vector y; in a backward cycle, transmitting an error signal S through arrays A and C and reading output vector z; updating array A by transmitting input vector x and error signal S through array A; in a forward cycle, transmitting an input vector ei through array A and reading output vector y′; calculating ƒ(y′) using y′; and updating array C by transmitting input vector ei and ƒ(y′) through array C. A DNN is also provided.

公开(公告)号：US10726895B1

公开(公告)日：2020-07-28

申请号：US16241606

申请日：2019-01-07

Applicant: International Business Machines Corporation

Inventor： Seyoung Kim ,  Tayfun Gokmen ,  Hyung-Min Lee ,  Wilfried Haensch

IPC: G06N3/063 ,  G06F13/18 ,  G11C11/00 ,  G11C11/56 ,  G11C11/16 ,  H01L27/22 ,  G11C16/28 ,  G11C13/00 ,  G11C15/00

Abstract: A system, comprising: a memory that stores computer-executable components; a processor, operably coupled to the memory, that executes the computer-executable components stored in the memory, wherein the computer-executable components comprise: an expression component that expresses the read current range in an RPU as read current Iwmin and Iwmax, a constant current source component that generates a reference current I, a computing component that subtracts the reference current value within from the read current value to generate an active net current read value that is negative, positive or null; a weighting component that analyzes the active current value and assigns it to a negative, positive or null weight.

公开(公告)号：US10664745B2

公开(公告)日：2020-05-26

申请号：US15196346

申请日：2016-06-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Tayfun Gokmen ,  Michael P. Perrone ,  Yurii A. Vlasov

IPC: G06N3/063 ,  G06N3/04 ,  G06N3/08

Abstract: An array of resistive processing units (RPUs) comprises a plurality of rows of RPUs and a plurality of columns of RPUs wherein each RPU comprises an AND gate configured to perform an AND operation of a first stochastic bit stream received from a first stochastic translator translating a number encoded from a neuron in a row and a second stochastic bit stream received from a second stochastic translator translating a number encoded from a neuron in a column. A first storage is configured to store a weight value of the RPU, and a second storage is configured to store an amount of change to the weight value of the RPU. When the first stochastic bit stream and the second stochastic bit stream coincide, the amount of change to the weight value of the RPU is added to the weight value of the RPU.

公开(公告)号：US20190354847A1

公开(公告)日：2019-11-21

申请号：US16362031

申请日：2019-03-22

Applicant: International Business Machines Corporation

Inventor： Malte Rasch ,  Tayfun Gokmen ,  Mattia Rigotti ,  Wilfried Haensch

IPC: G06N3/063 ,  G06N3/08 ,  G06T7/11

Abstract: Mechanisms are provided for acceleration of convolutional neural networks on analog arrays. Input ports receive image signals from frames in an input image. Input memory arrays store the image signals received from the input ports into a respective input memory location to create a plurality of image sub-regions in input memory arrays. A distributor associated each of a set of analog array tiles in an analog array to a part of image sub-regions of the input memory arrays, so that one or more of a set of analog memory components is associated with the image signals in a distribution order to create a respective output signal. An assembler stores each of the respective output signals into one of a set of memory outputs in an output order that is determined by the distribution order.