公开(公告)号：US20090141530A1

公开(公告)日：2009-06-04

申请号：US12110582

申请日：2008-04-28

申请人： Igor Arsovski ,  Michael T. Fragano ,  Rahul K. Nadkarni ,  Reid A. Wisort

发明人： Igor Arsovski ,  Michael T. Fragano ,  Rahul K. Nadkarni ,  Reid A. Wisort

IPC分类号： G11C15/04

CPC分类号： G11C15/04

摘要： A design structure embodied in a machine readable medium used in a design process includes a content addressable memory (CAM) device having an array of memory cells arranged in rows and columns; compare circuitry configured to indicate match results of search data presented to each row of the array; and compare circuitry configured to indicate match results of search data presented to each column of the array, thereby resulting in a two-dimensional search capability of the array.

摘要翻译： 体现在设计过程中使用的机器可读介质中的设计结构包括具有以行和列排列的存储单元阵列的内容寻址存储器（CAM）设备; 比较电路，被配置为指示呈现给阵列的每一行的搜索数据的匹配结果; 并且比较被配置为指示呈现给阵列的每列的搜索数据的匹配结果的电路，由此导致阵列的二维搜索能力。

公开(公告)号：US20090141528A1

公开(公告)日：2009-06-04

申请号：US11949065

申请日：2007-12-03

申请人： Igor Arsovski ,  Michael T. Fragano ,  Rahul K. Nadkarni ,  Reid A. Wistort

发明人： Igor Arsovski ,  Michael T. Fragano ,  Rahul K. Nadkarni ,  Reid A. Wistort

IPC分类号： G11C15/00

CPC分类号： G11C15/04

摘要： A content addressable memory (CAM) device includes an array of memory cells arranged in rows and columns; compare circuitry configured to indicate match results of search data presented to each row of the array; and compare circuitry configured to indicate match results of search data presented to each column of the array, thereby resulting in a two-dimensional search capability of the array.

摘要翻译： 内容可寻址存储器（CAM）设备包括以行和列布置的存储器单元阵列; 比较电路，被配置为指示呈现给阵列的每一行的搜索数据的匹配结果; 并且比较被配置为指示呈现给阵列的每列的搜索数据的匹配结果的电路，由此导致阵列的二维搜索能力。

公开(公告)号：US20090099828A1

公开(公告)日：2009-04-16

申请号：US11871198

申请日：2007-10-12

申请人： Igor Arsovski ,  Harold Pilo ,  Michael A. Ziegerhofer

发明人： Igor Arsovski ,  Harold Pilo ,  Michael A. Ziegerhofer

IPC分类号： G06F17/50 ,  G01R31/317

CPC分类号： G11C29/02 ,  G11C11/41 ,  G11C29/026 ,  G11C29/06 ,  G11C29/50 ,  G11C2029/5004

摘要： Disclosed are embodiments of a design structure for reducing and/or eliminating mismatch. The embodiments sample the bias of one or more circuit sub-components that require a balanced state (e.g., sampling the bias of the cross-coupled transistors in each memory cell and/or sense amp in a memory array) before chip burn-in, by initiating a burn-in process during which an individually selected state is applied to each of the devices in the circuit. This fatigues the devices away from their preferred states and towards a balanced state. The bias is periodically reassessed during the burn-in process to avoid over-correction. By using this method both memory cell and sense-amplifier mismatch can be reduced in memory arrays, resulting in smaller timing uncertainty and therefore faster memories.

摘要翻译： 公开了用于减少和/或消除失配的设计结构的实施例。 这些实施例在芯片烧录之前对需要平衡状态的一个或多个电路子部件（例如，在每个存储器单元中的交叉耦合晶体管的偏置和/或存储器阵列中的读出放大器）进行采样， 通过启动老化过程，在该过程中，单独选择的状态被应用于电路中的每个设备。 这使得设备远离其优选的状态并且朝向平衡状态。 在老化过程中定期重新评估偏差，以避免过度校正。 通过使用这种方法，可以在存储器阵列中减少存储器单元和读出放大器的失配，从而导致较小的定时不确定性，因此更快的存储器。

公开(公告)号：US07511528B2

公开(公告)日：2009-03-31

申请号：US11461788

申请日：2006-08-02

申请人： Igor Arsovski ,  Joseph A. Iadanza

发明人： Igor Arsovski ,  Joseph A. Iadanza

IPC分类号： H03K17/16 ,  H03K19/003

CPC分类号： H03K19/00346

摘要： A system and method for eliminating step response power supply perturbation during voltage island power-up/power-down on an integrated circuit is disclosed. An IC chip communicates with a primary power supply and includes at least one voltage island. A primary header on the voltage island of the chip communicates with the primary power supply via a primary header power path. A secondary header on the voltage island of the chip communicates with a secondary power supply via a secondary header power path. A control decoder communicating with the IC chip and the voltage island regulates the state of the primary and secondary headers.

摘要翻译： 公开了一种用于在集成电路上的电压岛上电/掉电期间消除阶跃响应电源扰动的系统和方法。 IC芯片与主电源通信并且包括至少一个电压岛。 芯片的电压岛上的主要头部通过主头电源路径与主电源通信。 芯片的电压岛上的次级标题通过辅助电源通路与二次电源通信。 与IC芯片和电压岛通信的控制解码器调节主集线器和副集线器的状态。

公开(公告)号：US20080253042A1

公开(公告)日：2008-10-16

申请号：US11735652

申请日：2007-04-16

申请人： Igor Arsovski

发明人： Igor Arsovski

IPC分类号： H02H3/30

CPC分类号： G11C17/16 ,  G11C17/18

摘要： An e-fuse circuit and a method of programming the e-fuse circuit method. The method includes in changing the threshold voltage of one selected field effect transistor of two field effect transistors connected to different storage nodes of the circuit so as to predispose the circuit place the storage nodes in predetermined and opposite states.

摘要翻译： 一种电子熔丝电路和一种编程电子熔丝电路方法。 该方法包括改变连接到电路的不同存储节点的两个场效应晶体管的一个选定的场效应晶体管的阈值电压，以便使电路将存储节点放置在预定和相反的状态。

公开(公告)号：US20080030223A1

公开(公告)日：2008-02-07

申请号：US11461788

申请日：2006-08-02

申请人： Igor Arsovski ,  Joseph A. Iadanza

发明人： Igor Arsovski ,  Joseph A. Iadanza

IPC分类号： H03K19/173

CPC分类号： H03K19/00346

摘要： A system and method for eliminating step response power supply perturbation during voltage island power-up/power-down on an integrated circuit is disclosed. An IC chip communicates with a primary power supply and includes at least one voltage island. A primary header on the voltage island of the chip communicates with the primary power supply via a primary header power path. A secondary header on the voltage island of the chip communicates with a secondary power supply via a secondary header power path. A control decoder communicating with the IC chip and the voltage island regulates the state of the primary and secondary headers.

摘要翻译： 公开了一种用于在集成电路上的电压岛上电/掉电期间消除阶跃响应电源扰动的系统和方法。 IC芯片与主电源通信并且包括至少一个电压岛。 芯片的电压岛上的主要头部通过主头电源路径与主电源通信。 芯片的电压岛上的次级标题通过辅助电源通路与二次电源通信。 与IC芯片和电压岛通信的控制解码器调节主集线器和副集线器的状态。

公开(公告)号：US20080025074A1

公开(公告)日：2008-01-31

申请号：US11763669

申请日：2007-06-15

申请人： Igor Arsovski

发明人： Igor Arsovski

IPC分类号： G11C15/04

CPC分类号： G11C7/067 ,  G11C7/12 ,  G11C15/04

摘要： A design structure for designing, manufacturing, or testing a content addressable memory (CAM) device. The CAM device includes a plurality of CAM cells, match-lines (MLs), search lines, and ML sense amplifiers. The ML sense amplifiers are capable of self-calibration to their respective thresholds to reduce effects of random device variation between adjacent sense amplifiers.

摘要翻译： 用于设计，制造或测试内容可寻址存储器（CAM）设备的设计结构。 CAM设备包括多个CAM单元，匹配线（ML），搜索线和ML读出放大器。 ML读出放大器能够对其各自的阈值进行自校准，以减少相邻读出放大器之间的随机器件变化的影响。

公开(公告)号：US07227766B2

公开(公告)日：2007-06-05

申请号：US11320746

申请日：2005-12-30

申请人： Igor Arsovski ,  Ali Sheikholeslami

发明人： Igor Arsovski ,  Ali Sheikholeslami

IPC分类号： G11C15/00

CPC分类号： G11C15/04

摘要： A low power matchline sensing scheme where power is distributed according to the number of mismatching bits occurring on a matchline is disclosed. In particular, match decisions involving a larger number of mismatched bits consume less power compared to match decisions having a lesser number of mismatched bits. The low power matchline sensing scheme is based upon a precharge-to-miss sensing architecture, and includes a current control circuit coupled to each matchline of the content addressable memory array for monitoring the voltage level of the matchline during a search operation. The current control circuit provides a voltage control signal to the current source of the matchline to adjust the amount of current applied to the matchline in response to the voltage of the matchline. In otherwords, matchlines that are slow to reach the match threshold voltage due to the presence of one or more mismatching bits will receive less current than matchlines having no mismatching bits. Significant power reduction without compromising search speed is realized since matchlines carrying a match result are provided with the maximum amount of current.

摘要翻译： 公开了一种低功率匹配线感测方案，其功率根据在匹配线上出现的不匹配比特数分布。 特别地，与具有较少数目不匹配位的匹配决策相比，涉及较大数目不匹配位的匹配决策消耗较少功率。 低功率匹配线感测方案基于预充电到缺失感测架构，并且包括耦合到内容可寻址存储器阵列的每个匹配线的电流控制电路，用于在搜索操作期间监视匹配线的电压电平。 电流控制电路向匹配线的电流源提供电压控制信号，以响应于匹配线的电压来调整施加到匹配线的电流量。 换句话说，由于存在一个或多个失配位而缓慢达到匹配阈值电压的匹配线将比不具有不匹配位的匹配线接收更少的电流。 由于具有匹配结果的匹配线具有最大电流量，所以实现了显着的功率降低而不影响搜索速度。

公开(公告)号：US07006368B2

公开(公告)日：2006-02-28

申请号：US10702489

申请日：2003-11-07

申请人： Igor Arsovski ,  Ali Sheikholeslami

发明人： Igor Arsovski ,  Ali Sheikholeslami

IPC分类号： G11C15/00

CPC分类号： G11C15/04

摘要： A low power matchline sensing scheme where power is distributed according to the number of mismatching bits occurring on a matchline is disclosed. In particular, match decisions involving a larger number of mismatched bits consume less power compared to match decisions having a lesser number of mismatched bits. The low power matchline sensing scheme is based upon a precharge-to-miss sensing architecture, and includes a current control circuit coupled to each matchline of the content addressable memory array for monitoring the voltage level of the matchline during a search operation. The current control circuit provides a voltage control signal to the current source of the matchline to adjust the amount of current applied to the matchline in response to the voltage of the matchline. In otherwords, matchlines that are slow to reach the match threshold voltage due to the presence of one or more mismatching bits will receive less current than matchlines having no mismatching bits. Significant power reduction without compromising search speed is realized since matchlines carrying a match result are provided with the maximum amount of current.

摘要翻译： 公开了一种低功率匹配线感测方案，其功率根据在匹配线上出现的不匹配比特数分布。 特别地，与具有较少数目不匹配位的匹配决策相比，涉及较大数目不匹配位的匹配决策消耗较少功率。 低功率匹配线感测方案基于预充电到缺失感测架构，并且包括耦合到内容可寻址存储器阵列的每个匹配线的电流控制电路，用于在搜索操作期间监视匹配线的电压电平。 电流控制电路向匹配线的电流源提供电压控制信号，以响应于匹配线的电压来调整施加到匹配线的电流量。 换句话说，由于存在一个或多个失配位而缓慢达到匹配阈值电压的匹配线将比不具有不匹配位的匹配线接收更少的电流。 由于具有匹配结果的匹配线具有最大电流量，所以实现了显着的功率降低而不影响搜索速度。