公开(公告)号：US20060265363A1

公开(公告)日：2006-11-23

申请号：US11457952

申请日：2006-07-17

申请人： Jean Calvignac ,  Gordon Davis ,  Marco Heddes ,  Michael Siegel

发明人： Jean Calvignac ,  Gordon Davis ,  Marco Heddes ,  Michael Siegel

IPC分类号： G06F17/30

CPC分类号： H04L49/3009 ,  G11C15/00 ,  H04L45/745 ,  H04L45/7453 ,  H04L49/90

摘要： A method and system for identifying a data structure associated with a packet of data. A processor internal to a packet processor may extract one or more fields in a packet header field of a received packet of data to generate a search key. The internal processor may then be configured to select which table, e.g., routing table, quality of service table, filter table, needs to be accessed using the search key in order to process the received packet of data. A determination may then be made by the internal processor as to whether a CAM or a hash table and a Patricia Tree are used to identify the data structure associated with the received packet of data. Based on table definitions in a register, the internal processor may make such a determination.

摘要翻译： 一种用于识别与数据包相关联的数据结构的方法和系统。 分组处理器内部的处理器可以提取接收到的数据分组的分组报头字段中的一个或多个字段以生成搜索关键字。 然后可以将内部处理器配置为选择哪个表，例如路由表，服务质量表，过滤表，需要使用搜索关键字进行访问，以便处理接收的数据分组。 然后内部处理器可以确定CAM或散列表和Patricia Tree是否用于标识与所接收的数据分组相关联的数据结构。 根据寄存器中的表定义，内部处理器可以作出这样的确定。

公开(公告)号：US20060173831A1

公开(公告)日：2006-08-03

申请号：US11353841

申请日：2006-02-14

申请人： Claude Basso ,  Jean Calvignac ,  Gordon Davis ,  Piyush Patel

发明人： Claude Basso ,  Jean Calvignac ,  Gordon Davis ,  Piyush Patel

IPC分类号： G06F17/30

CPC分类号： H04L45/00 ,  G06F17/30985 ,  H04L12/66 ,  H04L45/745 ,  H04L45/7457 ,  Y10S707/99933 ,  Y10S707/99935 ,  Y10S707/99936

摘要： A method and apparatus are used for finding the longest prefix match in a variable length prefix search when searching a direct table within a routing table structure of a network processor. The search through the routing table structure is expedited by hashing a first segment of an internet protocol address with a virtual private network number followed by concatenating the unhashed bits of the IP address to the result of the hash operation to form an input key. Patterns are compared a bit at a time until an exact match or the best match is found. The search is conducted in a search tree that provides that the matching results will be the best possible match.

摘要翻译： 当在网络处理器的路由表结构中搜索直接表时，使用方法和装置来在可变长度前缀搜索中找到最长的前缀匹配。 通过路由表结构的搜索是通过用互联网协议地址的第一段与虚拟专用网络号进行散列加速，然后将IP地址的未分配比特连接到散列操作的结果以形成输入密钥。 模式一次比较一点，直到找到完全匹配或最佳匹配。 搜索在搜索树中进行，其提供匹配结果将是最佳匹配。

公开(公告)号：US5325404A

公开(公告)日：1994-06-28

申请号：US836492

申请日：1992-02-18

申请人： Jean-Claude Bigey ,  Jean Calvignac ,  Jean-Christophe Debos ,  Rene Gallezot ,  Eric Saint-Georges

发明人： Jean-Claude Bigey ,  Jean Calvignac ,  Jean-Christophe Debos ,  Rene Gallezot ,  Eric Saint-Georges

IPC分类号： H04J3/06 ,  H04L7/00 ,  H04Q11/04

CPC分类号： H04J3/062 ,  H04Q11/04

摘要： In a communication node (10) which comprises switching device (24) operating under control of a clock signal of period T for exchanging information slots carried in external frames of period T' comprising n slots, with each slot comprising a x-bit data byte, between external Time Division Multiplex TDM links (12,14) attached to the communication node, a synchronization device prevents the slippage phenomena due to the asynchronies between T and T' from causing a loss of data slots by generating at the input of the switching means internal frames from the received external frames. These internal frames are synchronous with the clock signal of period T and have a format which allows the slippage to be compensated.

摘要翻译： 在包括在周期T的时钟信号的控制下操作的交换设备（24）的通信节点（10）中，用于交换在包括n个时隙的周期T'的外部帧中携带的信息时隙，每个时隙包括x位数据字节 ，在连接到通信节点的外部时分复用TDM链路（12,14）之间，同步设备防止由于T和T'之间的异步而导致的数据时隙的丢失导致在切换的输入处产生的滑动现象 指从接收的外部帧的内部帧。 这些内部帧与周期T的时钟信号同步，并具有允许补偿滑动的格式。

公开(公告)号：US5119478A

公开(公告)日：1992-06-02

申请号：US357225

申请日：1989-05-26

申请人： Jean Calvignac ,  Jacques Feraud ,  Bernard Naudin ,  Claude Pin ,  Eric Saint-Georges

发明人： Jean Calvignac ,  Jacques Feraud ,  Bernard Naudin ,  Claude Pin ,  Eric Saint-Georges

IPC分类号： H04L29/02 ,  H04L29/06 ,  H04L29/08

CPC分类号： H04L29/06 ,  H04L69/12 ,  H04L69/324

摘要： The bit streams, transporting the frames, received from lines (6) are placed in register 12 in such a way that n bits are processed in parallel during a time interval T. Parallel processor 10 counts the consecutive logical "1" bits beginning at the low order (left most) bit of the n bits received in interval T and from the bits received in the previous interval T-1, to determine when this number is found equal to 5 which bits have to be deleted, and when this number is found equal to 6 whether a flag is received. As a result, it reassembles N-bit characters, with N

公开(公告)号：US5119376A

公开(公告)日：1992-06-02

申请号：US506035

申请日：1990-04-06

申请人： Mohamed Badaoui ,  Jean Calvignac ,  Guy Carle ,  Christian Garcia ,  Pierre Vachee

发明人： Mohamed Badaoui ,  Jean Calvignac ,  Guy Carle ,  Christian Garcia ,  Pierre Vachee

IPC分类号： H04L29/10 ,  G06F13/38

CPC分类号： G06F13/385

摘要： Interconnection system for attaching a maximum number n of equipment users EU (DCE or DTE) to the line adapter (2) of a communication processing unit. The user data and control bits are carried on transmit and receive serial link 4 and 6 in data and control slot entities arranged in frame of period T, comprising one entity per user. These entities are allocated to the user equipments through multiplexing/demultiplexing circuit (10), link adapters (12-1) to (12-8) and connecting boxes (30-1) to (30-8). The user equipments are connected through active remote modules which are specific to the standardized interfaces of the user equipments. Link adapters (12-1) to (12-8) add to the data and control slot entities an outband slot which is used for exchanging control information, such as the active remote module address and type which are stored in memory (42), to be transmitted to the line adapter (2). The advantage of the interconnection system is that the attachment of the user equipments is simplified.

摘要翻译： 用于将最多数量的设备用户EU（DCE或DTE）附加到通信处理单元的线路适配器（2）的互连系统。 用户数据和控制位在周期T的帧中布置的数据和控制时隙实体中的发送和接收串行链路4和6上承载，每个用户包括一个实体。 这些实体通过复用/解复用电路（10），链路适配器（12-1）至（12-8）和连接盒（30-1）至（30-8）分配给用户设备。 用户设备通过用户设备标准接口专用的主动远程模块连接。 链路适配器（12-1）至（12-8）向数据和控制时隙实体添加用于交换诸如存储在存储器（42）中的主动远程模块地址和类型的控制信息的外带时隙， 被传送到线路适配器（2）。 互连系统的优点是简化了用户设备的连接。

公开(公告)号：US4799219A

公开(公告)日：1989-01-17

申请号：US77484

申请日：1987-07-24

申请人： Jean Calvignac ,  Pierre Secondo

发明人： Jean Calvignac ,  Pierre Secondo

IPC分类号： H04L12/64 ,  H04J3/26

CPC分类号： H04L12/64

摘要： A pseudo synchronous mechanism is used in the nodes of a communication network for exchanging non-character coded information (NCI) and potentially character coded information on inter node links. Communication is performed in frames comprising circuit slots devoted to the transportation of character coded information. The circuit slots are assigned to circuit users on a per-call basis under control of node management apparatus. The slots are qualified by at least one qualification bit (Caq) which indicates, when set to a first value (0) that the users are momentarily active and when set to a second value (1) that the users are momentarily inactive. The node mechanism includes a store in which queues of storing positions are assigned to the circuit users attached to the node. The circuit user information to be sent on the network internode links or received from the internode links is stored in the store. The node mechanism further includes an internode adapter which controls the generation and reception of the frames to and from each internode link. The adapter operates under control of a node manager which assigns on a per-call basis, a set of at least one slot in the frames transported on the network link to each of a plurality of circuit users. The node also includes transmit and receive controls which cause the queues assigned to the plurality of local users to be sequentially scanned and read from or written to according to whether the qualification bits are set to a first value.

公开(公告)号：US4491913A

公开(公告)日：1985-01-01

申请号：US433744

申请日：1982-10-12

申请人： Jean Calvignac ,  Yves Granger ,  Andre Masclet

发明人： Jean Calvignac ,  Yves Granger ,  Andre Masclet

IPC分类号： H04L29/04 ,  G06F13/00 ,  G06F13/22 ,  G06F13/38 ,  G06F1/00

CPC分类号： G06F13/385 ,  G06F13/22

摘要： The address generating device is provided for a communication line scanning device. The lines are connected to the scanning device through n line interface circuits, n varying in accordance with the network configuration. Each interface circuit can be connected to a various number of lines, for instance one line or k lines in a preferred embodiment, and comprises means for providing to the address generating device, a presence indicating signal indicating that it is plugged and a signal indicating the number of the lines connected thereto. A first logic circuit receives the presence indicating signals as inputs and generates on its outputs the address bits of the last present interface circuit to be scanned. A first counter able to count in binary mode up to n-1 is incremented by an increment pulse provided by a clock on each period assigned to the scanning of a line. This counter outputs the address bits of the successive interface circuits. A comparator compares the address bits so generated and the address bits of the last present interface circuit to be scanned and outputs a reset signal when these bits are equal.

摘要翻译： 为通信线扫描装置提供地址产生装置。 线路通过n线接口电路连接到扫描设备，n根据网络配置而变化。 每个接口电路可以连接到各种数量的线路，例如在优选实施例中的一条线路或k条线路，并且包括用于向地址生成设备提供指示其被插入的存在指示信号的装置和指示其的信号 与其连接的线数。 第一逻辑电路接收存在指示信号作为输入，并在其输出上产生要扫描的最后一个当前接口电路的地址位。 能够以二进制模式计数直到n-1的第一个计数器由分配给扫描行的每个周期上的时钟提供的增量脉冲递增。 该计数器输出连续接口电路的地址位。 一个比较器比较这样产生的地址位和最后一个当前接口电路的地址位，并在这些位相等时输出一个复位信号。