利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

57 条记录 (耗时 0.028 秒)

    Priority based bandwidth allocation within real-time and non-real time traffic streams
    1.
    发明授权
    Priority based bandwidth allocation within real-time and non-real time traffic streams 有权
    实时和非实时业务流中基于优先级的带宽分配

    公开(公告)号：US07872968B2

    公开(公告)日：2011-01-18

    申请号：US11608295

    申请日：2006-12-08

    申请人： Brahmanand Kumar Gorti ,  Marco Heddes ,  Clark Debs Jeffries ,  Andreas Kind ,  Michael Steven Siegel

    发明人： Brahmanand Kumar Gorti ,  Marco Heddes ,  Clark Debs Jeffries ,  Andreas Kind ,  Michael Steven Siegel

    IPC分类号： G01R31/08 ,  H04L12/28

    CPC分类号： H04L47/6215 ,  H04L47/10 ,  H04L47/2416 ,  H04L47/2433 ,  H04L47/30 ,  H04L47/32 ,  H04L47/50 ,  H04L47/52 ,  H04L47/56

    摘要： A method and system for transmitting packets in a packet switching network. Packets received by a packet processor may be prioritized based on the urgency to process them. Packets that are urgent to be processed may be referred to as real-time packets. Packets that are not urgent to be processed may be referred to as non-real-time packets. Real-time packets have a higher priority to be processed than non-real-time packets. A real-time packet may either be discarded or transmitted into a real-time queue based upon its value priority, the minimum and maximum rates for that value priority and the current real-time queue congestion conditions. A non-real-time packet may either be discarded or transmitted into a non-real-time queue based upon its value priority, the minimum and maximum rates for that value priority and the current real-time and non-real-time queue congestion conditions.

    摘要翻译： 一种用于在分组交换网络中传送分组的方法和系统。 可以基于处理它们的紧急性来优先考虑由分组处理器接收的分组。 紧急处理的数据包可以称为实时数据包。 不紧急处理的数据包可能被称为非实时数据包。 实时数据包的优先级要高于非实时数据包。 可以根据其值优先级，该值优先级的最小和最大速率以及当前实时队列拥塞条件，将实时分组丢弃或传输到实时队列中。 可以基于其值优先级，该值优先级的最小和最大速率以及当前的实时和非实时队列拥塞将非实时分组丢弃或发送到非实时队列 条件。

    Semaphore management subsystem for use with multi-thread processor systems
    3.
    发明授权
    Semaphore management subsystem for use with multi-thread processor systems 失效
    用于多线程处理器系统的信号量管理子系统

    公开(公告)号：US07454753B2

    公开(公告)日：2008-11-18

    申请号：US10179860

    申请日：2002-06-25

    申请人： Gordon Taylor Davis ,  Marco Heddes ,  Steven Kenneth Jenkins ,  Ross Boyd Leavens ,  Robert Brian Likovich, Jr.

    发明人： Gordon Taylor Davis ,  Marco Heddes ,  Steven Kenneth Jenkins ,  Ross Boyd Leavens ,  Robert Brian Likovich, Jr.

    IPC分类号： G06F9/46 ,  G06F12/00 ,  G06F12/14 ,  G06F13/00 ,  G06F13/28

    CPC分类号： G06F9/52

    摘要： A generic method and apparatus for managing semaphores in a multi-threaded processing system has a storage area for each of the threads in the processing system. Each storage area includes a first part for storing at least one indicia for identifying at least one unique semaphore from a plurality of semaphores utilized by the multi-threaded processing system and a second part for storing an indicia for indicating a locked status for the stored semaphore. A thread requiring a semaphore sends a semaphore lock request to the semaphore manager which examines the contents of all of the storage areas to determine the status of the requested semaphore. If the requested semaphore is not locked, it is locked for the requesting thread by inserting the requested semaphore and locked status in the memory location assigned to the requesting thread.

    摘要翻译： 用于在多线程处理系统中管理信号量的通用方法和装置具有用于处理系统中的每个线程的存储区域。 每个存储区域包括第一部分，用于存储用于从多线程处理系统使用的多个信号量中识别至少一个唯一信号量的至少一个标记，以及用于存储用于指示所存储的信号量的锁定状态的标记的第二部分 。 需要信号量的线程向信号量管理器发送信号锁定请求，该信号量管理器检查所有存储区域的内容，以确定所请求的信号量的状态。 如果请求的信号量未被锁定，则通过将请求的信号量和锁定状态插入到分配给请求线程的存储器位置中来锁定请求线程。

    Network processor with single interface supporting tree search engine and CAM
    5.
    发明授权
    Network processor with single interface supporting tree search engine and CAM 失效
    具有单界面支持树搜索引擎和CAM的网络处理器

    公开(公告)号：US07167471B2

    公开(公告)日：2007-01-23

    申请号：US09940758

    申请日：2001-08-28

    申请人： Jean Louis Calvignac ,  Gordon Taylor Davis ,  Marco Heddes ,  Michael Steven Siegel

    发明人： Jean Louis Calvignac ,  Gordon Taylor Davis ,  Marco Heddes ,  Michael Steven Siegel

    IPC分类号： H04L12/56

    CPC分类号： H04L49/3009 ,  G11C15/00 ,  H04L45/745 ,  H04L45/7453 ,  H04L49/90

    摘要： A method and system for identifying a data structure associated with a packet of data. A processor internal to a packet processor may extract one or more fields in a packet header field of a received packet of data to generate a search key. The internal processor may then be configured to select which table, e.g., routing table, quality of service table, filter table, needs to be accessed using the search key in order to process the received packet of data. A determination may then be made by the internal processor as to whether a CAM or a hash table and a Patricia Tree are used to identify the data structure associated with the received packet of data. Based on table definitions in a register, the internal processor may make such a determination.

    摘要翻译： 一种用于识别与数据包相关联的数据结构的方法和系统。 分组处理器内部的处理器可以提取接收到的数据分组的分组报头字段中的一个或多个字段以生成搜索关键字。 然后可以将内部处理器配置为选择哪个表，例如路由表，服务质量表，过滤表，需要使用搜索关键字进行访问，以便处理接收的数据分组。 然后内部处理器可以确定CAM或散列表和Patricia Tree是否用于标识与所接收的数据分组相关联的数据结构。 根据寄存器中的表定义，内部处理器可以作出这样的确定。

    System method structure in network processor that indicates last data buffer of frame packet by last flag bit that is either in first or second position
    8.
    发明申请
    System method structure in network processor that indicates last data buffer of frame packet by last flag bit that is either in first or second position 失效
    网络处理器中的系统方法结构，通过最后一个标志位指示帧分组的最后数据缓冲区，处于第一或第二位置

    公开(公告)号：US20060101172A1

    公开(公告)日：2006-05-11

    申请号：US11320277

    申请日：2005-12-27

    申请人： Claude Basso ,  Jean Calvignac ,  Marco Heddes ,  Joseph Logan ,  Fabrice Verplanken

    发明人： Claude Basso ,  Jean Calvignac ,  Marco Heddes ,  Joseph Logan ,  Fabrice Verplanken

    IPC分类号： G06F5/00

    CPC分类号： H04L49/901 ,  H04L49/103 ,  H04L49/3018 ,  H04L49/90 ,  H04L49/9094

    摘要： A method and structure for determining when a frame of information comprised of one or more buffers of data being transmitted in a network processor has completed transmission is provided. The network processor includes several control blocks, one for each data buffer, each containing control information linking one buffer to another. Each control block has a last bit feature which is a single bit settable to “one or “zero” and indicates the transmission of when the data buffer having the last bit. The last bit is in a first position when an additional data buffer is to be chained to a previous data buffer indicating an additional data buffer is to be transmitted and a second position when no additional data buffer is to be chained to a previous data buffer. The position of the last bit is communicated to the network processor indicating the ending of a particular frame.

    摘要翻译： 提供了一种用于确定在网络处理器中正在发送的一个或多个数据缓冲器组成的信息帧何时完成传输的方法和结构。 网络处理器包括几个控制块，每个数据缓冲器一个，每个包含将一个缓冲器链接到另一个的控制信息。 每个控制块具有最后一位特征，其是可设置为“一个或”零“的单个位，并且指示何时数据缓冲器具有最后位，当最后一位处于第一位置时，当附加数据缓冲器为 被链接到先前的数据缓冲器，指示要发送附加数据缓冲器，并且当没有附加数据缓冲器被链接到先前的数据缓冲器时的第二位置，最后位的位置被传送到指示结束的网络处理器 的特定框架。

    Method and apparatus for implementing multiple configurable sub-busses of a point-to-point bus
    9.
    发明授权
    Method and apparatus for implementing multiple configurable sub-busses of a point-to-point bus 失效
    用于实现点对点总线的多个可配置子总线的方法和装置

    公开(公告)号：US06996650B2

    公开(公告)日：2006-02-07

    申请号：US10147682

    申请日：2002-05-16

    申请人： Jean Calvignac ,  Marco Heddes ,  Kerry Christopher Imming ,  Christopher Jon Johnson ,  Joseph Franklin Logan ,  Tolga Ozguner

    发明人： Jean Calvignac ,  Marco Heddes ,  Kerry Christopher Imming ,  Christopher Jon Johnson ,  Joseph Franklin Logan ,  Tolga Ozguner

    IPC分类号： G06F13/42 ,  G06F13/14 ,  G06F13/40

    CPC分类号： G06F13/4273 ,  G06F13/4059

    摘要： A method and apparatus are provided for implementing multiple configurable sub-busses of a point-to-point bus. Each of a plurality of bus interconnects include a transmit interface and a receive interface connected to the point-to-point bus. Each transmit interface includes a transmit buffer and a serializer coupled between the buffer and the point-to-point bus. The transmit buffer provides an asynchronous interface between a transmit source and the serializer. The serializer receives data and control signals from the transmit buffer at a first frequency and transmits data and control signals over the point-to-point bus at a higher second frequency. Transmit steering logic is coupled between the transmit source and each transmit buffer of the plurality of bus interconnects. Transmit steering logic directs data and control signals from transmit source to each selected one of the transmit buffers based upon a selected bus configuration.

    摘要翻译： 提供了一种用于实现点对点总线的多个可配置子总线的方法和装置。 多个总线互连中的每一个包括连接到点对点总线的发送接口和接收接口。 每个发送接口包括耦合在缓冲器和点到点总线之间的发送缓冲器和串行器。 发送缓冲区提供发送源和串行器之间的异步接口。 串行器以第一频率从发送缓冲器接收数据和控制信号，并以更高的第二频率在点对点总线上发送数据和控制信号。 发射导向逻辑耦合在多个总线互连的发射源和每个发射缓冲器之间。 发射导向逻辑基于所选择的总线配置将数据和控制信号从发射源引导到每个所选发射缓冲器中的一个。

    Method and system for compressing multi-field rule specifications
    10.
    发明申请
    Method and system for compressing multi-field rule specifications 失效
    压缩多场规则规范的方法和系统

    公开(公告)号：US20050237938A1

    公开(公告)日：2005-10-27

    申请号：US10832957

    申请日：2004-04-27

    申请人： Everett Corl ,  Gordon Davis ,  Marco Heddes ,  Piyush Patel ,  Ravinder Sabhikhi

    发明人： Everett Corl ,  Gordon Davis ,  Marco Heddes ,  Piyush Patel ,  Ravinder Sabhikhi

    IPC分类号： G01R31/08 ,  G06F11/00 ,  G06F15/18 ,  G06F17/00 ,  G06N5/02 ,  G08C15/00 ,  H04J1/16 ,  H04J3/14 ,  H04L1/00 ,  H04L12/26

    CPC分类号： G06N99/005

    摘要： The present invention relates to a method and system for storing a plurality of multi-field classification rules in a computer system. Each multi-field classification rule includes a rule specification that itself includes a plurality of fields and a plurality of field definitions corresponding to the fields. The method of the present invention includes providing a virtual rule table, where the table stores a plurality of field definitions, and for each of the plurality of multi-field classification rules, compressing the rule specification by replacing at least one field definition with an associated index into the virtual rule table. The method also includes storing each of the compressed rule specifications and the virtual rule table in a shared segment of memory.

    摘要翻译： 本发明涉及一种用于在计算机系统中存储多个多场分类规则的方法和系统。 每个多字段分类规则包括本身包括多个字段的规则规范和对应于字段的多个字段定义。 本发明的方法包括提供虚拟规则表，其中表存储多个字段定义，并且对于多个多字段分类规则中的每一个，通过用相关联的替换来替换至少一个字段定义来压缩规则规范 索引到虚拟规则表。 该方法还包括将每个压缩规则规范和虚拟规则表存储在存储器的共享段中。