公开(公告)号：US06490665B1

公开(公告)日：2002-12-03

申请号：US09350974

申请日：1999-07-09

Applicant: Jiin Lai ,  Chih-kuo Kao ,  Chia-Hsin Chen

Inventor： Jiin Lai ,  Chih-kuo Kao ,  Chia-Hsin Chen

IPC: G06F1200

CPC classification number: G06F12/0895 ,  G06F12/123

Abstract: A memory-access management method and system is provided for use with an SDRAM (Synchronous Dynamic Random-Access Memory) or the like, for the purpose of increasing the performance of memory access to the SDRAM by means of tracking the memory-access history of previous access operations. The memory-page management system includes a page-table register unit including a page table for storing a predefined number of recently accessed memory locations of the memory unit. Further, the memory-page management system includes a comparison unit capable of, in response to each access request to the memory unit, checking whether the requested memory location is a hit to any one stored in the page table in the page-table register unit. A utilization-rate register unit is coupled to the page-table register unit for monitoring the least-recently-used records stored in the page-table register unit; and moreover, a validity-checking unit is coupled to the page-table register unit for checking whether the address data stored in the page table in the page-table register unit is valid or invalid.

Abstract translation: 提供了一种与SDRAM（同步动态随机存取存储器）等一起使用的存储器访问管理方法和系统，用于通过跟踪存储器访问历史来增加对SDRAM的存储器访问的性能 以前的访问操作。 存储器页管理系统包括页表寄存器单元，其包括用于存储存储器单元的预定数量的最近访问的存储器位置的页表。 此外，存储器页管理系统包括：比较单元，其能够响应于对存储器单元的每个访问请求，检查所请求的存储器位置是否是存储在页表寄存器单元中的页表中的任何一个的命中 。 利用率寄存器单元耦合到页表寄存器单元，用于监视存储在页表寄存器单元中的最近最少使用的记录; 此外，有效性检查单元耦合到页表寄存器单元，用于检查存储在页表寄存器单元中的页表中的地址数据是有效还是无效。

公开(公告)号：US06269430B1

公开(公告)日：2001-07-31

申请号：US09342711

申请日：1999-06-29

Applicant: Chia-Hsin Chen ,  You-Ming Chiu ,  Jiin Lai

Inventor： Chia-Hsin Chen ,  You-Ming Chiu ,  Jiin Lai

IPC: G06F1200

CPC classification number: G06F12/0875 ,  G06F13/4243 ,  G06F2212/303

Abstract: A method for a CPU interface to control a writing process that writes data sent from a CPU to a memory. The CPU interface controls the writing process through steps mainly including receiving a write request and data from a CPU, sending a dummy request to the memory control circuit of the memory circuit, and then writing the data to a memory of the memory circuit. After the CPU interface receives a write request from the CPU, the CPU interface sends a dummy request to the memory control circuit to pre-charge and activate the designative memory page of the memory circuit before the data is sent to the memory circuit. Since the designative memory page is always pre-charged and activated while the data is received at the memory control circuit, the memory control circuit sends only a write command to the memory for writing the data to the memory without further pre-charging and activating the designative memory page. Therefore, the total number of clock cycles required for processing a write request is shortened.

Abstract translation: 一种CPU接口的方法，用于控制将从CPU发送到存储器的数据写入的写入过程。 CPU接口通过主要包括从CPU接收写入请求和数据，向存储器电路的存储器控​​制电路发送伪请求，然后将数据写入存储器电路的存储器的步骤来控制写入过程。 在CPU接口从CPU接收到写请求之后，CPU接口向存储器控制电路发送伪请求，以在数据被发送到存储器电路之前对存储器电路的指定存储器页进行预充电和激活。 由于在存储器控制电路中接收到数据时，指定存储器页面总是被预先充电并被激活，所以存储器控制电路仅将写入命令发送到存储器，用于将数据写入存储器，而无需进一步的预充电和激活 指定记忆页面。 因此，缩短了处理写请求所需的总时钟周期数。

公开(公告)号：US06202167B1

公开(公告)日：2001-03-13

申请号：US09099977

申请日：1998-06-19

Applicant: Jiin Lai ,  Heng-Chen Ho ,  Kuo-Ping Liu

Inventor： Jiin Lai ,  Heng-Chen Ho ,  Kuo-Ping Liu

IPC: G06F108

CPC classification number: G06F1/08

Abstract: A computer chip set is devised for use on a computer mother board with at least two clock rates including a first clock rate and a second clock rate for the purpose of converting an input signal referencing either the first or second clock rate to an output signal referencing the other clock rate. The first and second clock rates are in virtual synchronism and have a fixed ratio between them. The computer chip set utilizes a phase signal generator capable of generating a set of phase signals and a signal conversion logic circuit for generating the output signal referencing one of the first and second clock rates other than the one referenced by the input signal. This computer chip set can allow the computer mother board to be operated without waiting a state so that the data processing efficiency of the computer mother board can be enhanced. A multiplexer means used in the computer chip set of the invention has an output which is selectively multiplexed between the first clock rate and the second clock rate to serve as a third clock signal. This computer chip set allows the designer to use a slower clock rate to drive the DRAM.

Abstract translation: 计算机芯片组被设计为在具有至少两个时钟速率的计算机母板上使用，包括第一时钟速率和第二时钟速率，用于将参考第一或第二时钟速率的输入信号转换为参考的输出信号 另一个时钟速率。 第一和第二时钟速率是虚拟同步的，并且它们之间具有固定的比例。 计算机芯片组利用能够产生一组相位信号的相位信号发生器和信号转换逻辑电路，用于产生参考第一和第二时钟速率之一的输出信号，而不是由输入信号所参考的那个。 该计算机芯片组可以允许计算机母板在不等待状态的情况下操作，从而可以提高计算机母板的数据处理效率。 在本发明的计算机芯片组中使用的多路复用器装置具有在第一时钟速率和第二时钟速率之间选择性地多路复用以用作第三时钟信号的输出。 该计算机芯片组允许设计者使用较慢的时钟速率来驱动DRAM。

公开(公告)号：US06079027A

公开(公告)日：2000-06-20

申请号：US100515

申请日：1998-06-19

Applicant: Jiin Lai ,  Heng-Chen Ho ,  Kuo-Ping Liu

Inventor： Jiin Lai ,  Heng-Chen Ho ,  Kuo-Ping Liu

IPC: G06F1/08 ,  G06F1/04

CPC classification number: G06F1/08

Abstract: A computer chip set is devised for use on a computer mother board with at least two clock rates including a first clock rate and a second clock rate for the purpose of converting an input signal referencing either the first or second clock rate to an output signal referencing the other clock rate. The first and second clock rates are in virtual synchronism and have a fixed ratio between them. The computer chip set utilizes a phase signal generator capable of generating a set of phase signals and a signal conversion logic circuit for generating the output signal referencing one of the first and second clock rates other than the one referenced by the input signal. This computer chip set can allow the computer mother board to be operated without waiting a state so that the data processing efficiency of the computer mother board can be enhanced. A multiplexer means used in the computer chip set of the invention has an output which is selectively muliplexed between the first clock rate and the second clock rate to serve as a third clock signal. This computer chip set allows the designer to use a slower clock rate to drive the DRAM.

Abstract translation: 计算机芯片组被设计为在具有至少两个时钟速率的计算机母板上使用，包括第一时钟速率和第二时钟速率，用于将参考第一或第二时钟速率的输入信号转换为参考的输出信号 另一个时钟速率。 第一和第二时钟速率是虚拟同步的，并且它们之间具有固定的比例。 计算机芯片组利用能够产生一组相位信号的相位信号发生器和信号转换逻辑电路，用于产生参考第一和第二时钟速率之一的输出信号，而不是由输入信号所参考的那个。 该计算机芯片组可以允许计算机母板在不等待状态的情况下操作，从而可以提高计算机母板的数据处理效率。 在本发明的计算机芯片组中使用的多路复用器装置具有在第一时钟速率和第二时钟速率之间选择性地混合以用作第三时钟信号的输出。 该计算机芯片组允许设计者使用较慢的时钟速率来驱动DRAM。