公开(公告)号：US06202167B1

公开(公告)日：2001-03-13

申请号：US09099977

申请日：1998-06-19

申请人： Jiin Lai ,  Heng-Chen Ho ,  Kuo-Ping Liu

发明人： Jiin Lai ,  Heng-Chen Ho ,  Kuo-Ping Liu

IPC分类号： G06F108

CPC分类号： G06F1/08

摘要： A computer chip set is devised for use on a computer mother board with at least two clock rates including a first clock rate and a second clock rate for the purpose of converting an input signal referencing either the first or second clock rate to an output signal referencing the other clock rate. The first and second clock rates are in virtual synchronism and have a fixed ratio between them. The computer chip set utilizes a phase signal generator capable of generating a set of phase signals and a signal conversion logic circuit for generating the output signal referencing one of the first and second clock rates other than the one referenced by the input signal. This computer chip set can allow the computer mother board to be operated without waiting a state so that the data processing efficiency of the computer mother board can be enhanced. A multiplexer means used in the computer chip set of the invention has an output which is selectively multiplexed between the first clock rate and the second clock rate to serve as a third clock signal. This computer chip set allows the designer to use a slower clock rate to drive the DRAM.

摘要翻译： 计算机芯片组被设计为在具有至少两个时钟速率的计算机母板上使用，包括第一时钟速率和第二时钟速率，用于将参考第一或第二时钟速率的输入信号转换为参考的输出信号 另一个时钟速率。 第一和第二时钟速率是虚拟同步的，并且它们之间具有固定的比例。 计算机芯片组利用能够产生一组相位信号的相位信号发生器和信号转换逻辑电路，用于产生参考第一和第二时钟速率之一的输出信号，而不是由输入信号所参考的那个。 该计算机芯片组可以允许计算机母板在不等待状态的情况下操作，从而可以提高计算机母板的数据处理效率。 在本发明的计算机芯片组中使用的多路复用器装置具有在第一时钟速率和第二时钟速率之间选择性地多路复用以用作第三时钟信号的输出。 该计算机芯片组允许设计者使用较慢的时钟速率来驱动DRAM。

公开(公告)号：US06079027A

公开(公告)日：2000-06-20

申请号：US100515

申请日：1998-06-19

申请人： Jiin Lai ,  Heng-Chen Ho ,  Kuo-Ping Liu

发明人： Jiin Lai ,  Heng-Chen Ho ,  Kuo-Ping Liu

IPC分类号： G06F1/08 ,  G06F1/04

CPC分类号： G06F1/08

摘要： A computer chip set is devised for use on a computer mother board with at least two clock rates including a first clock rate and a second clock rate for the purpose of converting an input signal referencing either the first or second clock rate to an output signal referencing the other clock rate. The first and second clock rates are in virtual synchronism and have a fixed ratio between them. The computer chip set utilizes a phase signal generator capable of generating a set of phase signals and a signal conversion logic circuit for generating the output signal referencing one of the first and second clock rates other than the one referenced by the input signal. This computer chip set can allow the computer mother board to be operated without waiting a state so that the data processing efficiency of the computer mother board can be enhanced. A multiplexer means used in the computer chip set of the invention has an output which is selectively muliplexed between the first clock rate and the second clock rate to serve as a third clock signal. This computer chip set allows the designer to use a slower clock rate to drive the DRAM.

摘要翻译： 计算机芯片组被设计为在具有至少两个时钟速率的计算机母板上使用，包括第一时钟速率和第二时钟速率，用于将参考第一或第二时钟速率的输入信号转换为参考的输出信号 另一个时钟速率。 第一和第二时钟速率是虚拟同步的，并且它们之间具有固定的比例。 计算机芯片组利用能够产生一组相位信号的相位信号发生器和信号转换逻辑电路，用于产生参考第一和第二时钟速率之一的输出信号，而不是由输入信号所参考的那个。 该计算机芯片组可以允许计算机母板在不等待状态的情况下操作，从而可以提高计算机母板的数据处理效率。 在本发明的计算机芯片组中使用的多路复用器装置具有在第一时钟速率和第二时钟速率之间选择性地混合以用作第三时钟信号的输出。 该计算机芯片组允许设计者使用较慢的时钟速率来驱动DRAM。

公开(公告)号：US06463013B1

公开(公告)日：2002-10-08

申请号：US09631293

申请日：2000-08-02

申请人： Kuo-Ping Liu ,  Jiin Lai ,  Jyh-fong Lin ,  Yu-Wei Lin

发明人： Kuo-Ping Liu ,  Jiin Lai ,  Jyh-fong Lin ,  Yu-Wei Lin

IPC分类号： G04F500

CPC分类号： H03L7/199 ,  G06F1/06 ,  H03L7/07 ,  H03L7/23

摘要： A clock generating apparatus and method for generating clock signals of different frequency. The clock generating apparatus and method receives and divides a main clock signal to obtain a reference clock signal. Then, the reference clock signal and the first feedback clock signal are phase-locked to obtain the first clock signal. Moreover, the reference clock signal and the second feedback clock signal are phase-locked to obtain the second clock signal. The reset signal and the first clock signal are received by a divider. The divider then outputs the first feedback clock signal. Another divider receives the reset signal and the second clock signal and then outputs the second feedback clock signal.

摘要翻译： 一种用于产生不同频率的时钟信号的时钟产生装置和方法。 时钟发生装置和方法接收和分割主时钟信号以获得参考时钟信号。 然后，参考时钟信号和第一反馈时钟信号被锁相以获得第一时钟信号。 此外，参考时钟信号和第二反馈时钟信号被锁相以获得第二时钟信号。 复位信号和第一时钟信号由分频器接收。 然后分频器输出第一反馈时钟信号。 另一分频器接收复位信号和第二时钟信号，然后输出第二反馈时钟信号。

公开(公告)号：US06400197B2

公开(公告)日：2002-06-04

申请号：US09766952

申请日：2001-01-22

申请人： Jiin Lai ,  Hsin-Chieh Lin ,  Kuo-Ping Liu

发明人： Jiin Lai ,  Hsin-Chieh Lin ,  Kuo-Ping Liu

IPC分类号： H03L700

CPC分类号： G06F5/06 ,  G06F1/10 ,  G06F2205/104 ,  H03L7/0814

摘要： A signal delay device having an internal delay lock loop for calibrating the delay interval. The signal delay device receives an input signal and then outputs the signal after a pre-defined delay period. The input signal varies according to a reference clock signal, and the required delay period is a quarter cycle of the clock signal. The delay device includes a multiplexer, an inverter, a phase detector, a counter and a delay element. During calibration, the phase detector, the counter and the delay element form a delay lock loop that can set up the delay time automatically.

摘要翻译： 一种具有用于校准延迟间隔的内部延迟锁定环路的信号延迟装置。 信号延迟装置接收输入信号，然后在预定义的延迟周期之后输出信号。 输入信号根据参考时钟信号而变化，所需的延迟周期是时钟信号的四分之一周期。 延迟装置包括多路复用器，反相器，相位检测器，计数器和延迟元件。 在校准期间，相位检测器，计数器和延迟元件形成可以自动设置延迟时间的延迟锁定环。

公开(公告)号：US07233134B2

公开(公告)日：2007-06-19

申请号：US10846569

申请日：2004-05-17

申请人： Kent Huang ,  Liang-Pin Tai ,  Hung-I Wang ,  Jian-Rong Huang ,  Kuo-Ping Liu ,  Yu-Fan Liao

发明人： Kent Huang ,  Liang-Pin Tai ,  Hung-I Wang ,  Jian-Rong Huang ,  Kuo-Ping Liu ,  Yu-Fan Liao

IPC分类号： G05F1/40

CPC分类号： H02M3/158

摘要： A DC-to-DC converter comprises a sense circuit to sense the output voltage of the converter to generate a feedback signal, a transconductive amplifier to amplify a difference between the feedback signal and a threshold signal to generate a first current and to generate a second current in response to a load transient, a charging circuit connected with the first current to generate a charging voltage, a driver to compare the charging voltage with two reference signals to generate a pair of low-side and high-side driving signals, and a fast response circuit to compare a load transient signal corresponding to the second current with a third reference signal to generate a bypass signal to drive the output stage of the converter in the load transient.

摘要翻译： DC-DC转换器包括用于感测转换器的输出电压以产生反馈信号的感测电路，用于放大反馈信号和阈值信号之间的差异的跨导放大器以产生第一电流并产生第二电流 响应于负载瞬变的电流，与第一电流连接以产生充电电压的充电电路，将充电电压与两个参考信号进行比较的驱动器，以产生一对低侧和高侧驱动信号，以及 快速响应电路，将与第二电流相对应的负载瞬态信号与第三参考信号进行比较，以产生旁路信号，以在负载瞬变中驱动转换器的输出级。

公开(公告)号：US07073047B2

公开(公告)日：2006-07-04

申请号：US10064454

申请日：2002-07-17

申请人： Kuang-Kai Kuo ,  Kuo-Ping Liu

发明人： Kuang-Kai Kuo ,  Kuo-Ping Liu

IPC分类号： G06F12/00

CPC分类号： G06F13/1631

摘要： A control chip and operating method for accelerating memory access that can be applied to a memory system whose memory read command actual address is read from a system bus in a number of synchronous transmissions. On receiving a first section read address, the control chip operates to compare the first section read address with an identical bit portion of the write address of the memory-write commands inside a memory-write command queue. If the comparison indicates some difference, permission for executing the memory read command is granted. If the comparison indicates the presence of identical bits, a second section read address is received and compared with an identical bit portion of the write address of the memory-write commands inside a memory-write command queue. If the comparison indicates some difference, permission for executing the memory read command is granted. If the comparison indicates the presence of identical bits, permission for executing the memory read command is granted only after the memory-write command inside the memory-write command queue having an identical write address is executed.

公开(公告)号：US20050258813A1

公开(公告)日：2005-11-24

申请号：US10850164

申请日：2004-05-21

申请人： Liang-Pin Tai ,  Kent Hwang ,  Jian-Rong Huang ,  Kuo-Ping Liu ,  Cheng-Hsuan Fan ,  Ko-Cheng Wang ,  Yu-Fan Liao

发明人： Liang-Pin Tai ,  Kent Hwang ,  Jian-Rong Huang ,  Kuo-Ping Liu ,  Cheng-Hsuan Fan ,  Ko-Cheng Wang ,  Yu-Fan Liao

IPC分类号： G05F1/40 ,  G05F1/44 ,  H02M1/08

CPC分类号： H02M1/08

摘要： A pulse width modulator includes an amplifier module, a comparator module, and a filter module. The amplifier module receives a feedback voltage signal from a passive network, and generates first and second non-inverted voltage signals and first and second inverted voltage signals in response to the feedback voltage signal. The comparator module receives the first and second non-inverted voltage signals and the first and second inverted voltage signals, and provides first and second differential voltage signals corresponding to the first and second non-inverted voltage signals and the first and second inverted voltage signals. The filter module is coupled between the amplifier module and the comparator module, and is operable so as to attenuate high frequency components of the first and second non-inverted voltage signals. As such, the presence of noise in the feedback voltage signal does not affect differential operation of the comparator module.

摘要翻译： 脉冲宽度调制器包括放大器模块，比较器模块和滤波器模块。 放大器模块从无源网络接收反馈电压信号，并响应于反馈电压信号产生第一和第二非反相电压信号以及第一和第二反相电压信号。 比较器模块接收第一和第二非反相电压信号以及第一和第二反相电压信号，并提供对应于第一和第二非反相电压信号以及第一和第二反相电压信号的第一和第二差分电压信号。 滤波器模块耦合在放大器模块和比较器模块之间，并且可操作以便衰减第一和第二非反相电压信号的高频分量。 因此，反馈电压信号中的噪声的存在不会影响比较器模块的差分工作。

公开(公告)号：US08525505B2

公开(公告)日：2013-09-03

申请号：US12766246

申请日：2010-04-23

申请人： Ko-Cheng Wang ,  Kuo-Ping Liu ,  Chih-Wei Tseng

发明人： Ko-Cheng Wang ,  Kuo-Ping Liu ,  Chih-Wei Tseng

IPC分类号： G05F1/575

CPC分类号： H02M3/1588 ,  H02M1/14 ,  Y02B70/1466

摘要： A PWM controller and control method for a DC-DC voltage converter filter the high-frequency component of the voltage at the phase node between high-side and low-side elements of the voltage converter to generate a signal synchronous and in phase or out-of-phase with the inductor current of the voltage converter, to achieve a low-ripple output voltage and stable loop control.

摘要翻译： 用于DC-DC电压转换器的PWM控制器和控制方法对电压转换器的高侧和低侧元件之间的相位节点处的电压的高频分量进行滤波，以产生同步和相位或相位的信号， 与电压转换器的电感电流相位，实现低纹波输出电压和稳定的环路控制。

公开(公告)号：US07023253B2

公开(公告)日：2006-04-04

申请号：US10882159

申请日：2004-07-02

申请人： Jian-Rong Huang ,  Kuo-Ping Liu ,  Kent Huang ,  Liang-Pin Tai

发明人： Jian-Rong Huang ,  Kuo-Ping Liu ,  Kent Huang ,  Liang-Pin Tai

IPC分类号： H03K5/00

CPC分类号： H03F3/217 ,  H02M3/1588 ,  H03K7/08 ,  Y02B70/1466

摘要： In a noise sensitivity improved switching system and method thereof, comprised sensing the output voltage of the switching system to generate a feedback signal, respectively amplifying the feedback signal by two gains to generate two signals in phase or out of phase, filtering one of the two amplified signals, and summing or comparing the filtered signal and the other one, thereby reducing the noise interference to the switching system.

摘要翻译： 在噪声敏感度改进的开关系统及其方法中，包括感测开关系统的输出电压以产生反馈信号，分别通过两个增益来放大反馈信号以产生相或异相的两个信号，滤波两个 放大信号，并对滤波后的信号进行求和或比较，从而降低对交换系统的噪声干扰。

公开(公告)号：US06946823B2

公开(公告)日：2005-09-20

申请号：US10846601

申请日：2004-05-17

申请人： Kent Huang ,  Liang-Pin Tai ,  Hung-I Wang ,  Jian-Rong Huang ,  Kuo-Ping Liu ,  Yu-Fan Liao

发明人： Kent Huang ,  Liang-Pin Tai ,  Hung-I Wang ,  Jian-Rong Huang ,  Kuo-Ping Liu ,  Yu-Fan Liao

IPC分类号： H02M3/158 ,  G05F1/575

CPC分类号： H02M3/1588 ,  Y02B70/1466

摘要： A delta-sigma DC-to-DC converter comprises a pair of high-side and low-side switches switched to convert an input voltage to an output voltage, a sense circuit to sense the output voltage of the converter to generate a feedback signal, a transconductive amplifier to amplify a difference between the feedback signal and a threshold signal to generate a differential current, a charging circuit connected with the differential current to generate a charging voltage, and a driver to compare the charging voltage with two reference signals to generate the pair of low-side and high-side driving signals.

摘要翻译： Δ-ΣDC-DC转换器包括一对开关将输入电压转换为输出电压的高侧和低侧开关，感测电路以感测转换器的输出电压以产生反馈信号， 用于放大反馈信号和阈值信号之间的差异以产生差分电流的跨导放大器，与差分电流连接以产生充电电压的充电电路，以及将充电电压与两个参考信号进行比较的驱动器，以产生 一对低侧和高侧驱动信号。