摘要:
A memory clock generator apparatus and method are implemented. The memory clock is generated, “open loop,” from a processor clock. The processor clock is gated into, and propagated through a shift register. A set of outputs tapped off of the shift register is decoded, along with a plurality of control signals, in AND-OR logic to generate a clock output, which may run at a predetermined multiple of the memory clock rate. The clock output may have one of a plurality of ratios of memory clock period to processor clock period. The control signals select the ratio. The clock generator may be started asynchronously, and, additionally, the generator outputs a signal to the processor having an edge that has a predetermined temporal relationship with the start of the clock generator.
摘要:
Video data (default data in case of a black original) output from a CCD line sensor 405 upon reading an image while a light source is kept OFF corresponds to beat noise contained in video data obtained upon reading an image while the light source is ON. After the beat noise data is stored, the correction data stored in a correction data storage unit is subtracted from video data read by a normal technique while the light source is ON in a correction memory, thus executing correction for removing beat noise. After the beat noise is removed in this way, when an image is formed under the control of a printer control unit, an image free from any beat noise can be obtained as an output image.
摘要:
A method is provided for use on a PCI-compliant (Peripheral Component Inter-connection) interface card having a UART (Universal Asynchronous Receiver-Transmitter) unit to generate a near-1.8432 MHz clock signal for clocking the UART unit. This method includes a first step of dividing a selected PCI clock signals, such as the 33 MHz PCI clock signal, from the PCI local bus by a predetermined integer frequency divisor; and a second step of multiplying the resulted frequency from the division by a predetermined integer frequency multiplier that allows the resulted frequency to be substantially close to 1.8432 MHz to serve as the intended clock signal to the UART unit. Preferably, the integer frequency multiplier is in the range equal to or greater than 8. This method can generate a more precise clock signal for the UART unit on the PCI-compliant interface card without having to use an external crystal oscillator. Moreover, the method requires only a frequency divider without a frequency multiplier to implement. The method allows the resulted frequency deviation to be smaller than the prior art and also allows a reduction in the implementation cost as compared to the prior art.
摘要:
A system clock switch circuit for a computer main board sends a reset signal to the chipset from the clock generator or a additional reset signal generator as soon as the system clock frequency is changed by the CPU. In result, the computer main board restarts with a new system clock frequency after the reset signal is canceled to avoid the malfunctions caused by the non-synchronization between the system clock frequency and the clock frequencies of peripherals.
摘要:
A clock generation circuit of the present invention extracts a phase error signal of a digital signal obtained from a recording medium (1) by a phase comparator (4), filters the phase error signal by a loop filter (5). In a first embodiment it converts the signal into an analog signal by a minute control D/A converter (6), detects whether the signal is within a set range by a range detector (9), generates a modulation reference signal by a modulation reference signal generator (10), modulates the modulation reference signal by a pulse width modulator (11), adds a frequency set value and the modulation reference signal by an adder (12), converts the addition result into an analog signal by a rough control D/A converter (13), cuts high-band components of the analog signal by a low-pass filter (14), adds the analog signals output from the minute control D/A converter (6) and the low-pass filter (14) by an analog adder (7), and outputs a clock signal by a voltage controlled oscillator (8) on the basis of an output signal of the analog adder (7). Thereby, a clock signal which can continuously lock a wide frequency range can be generated. In a second embodiment the loop filter output is oversampled (15), then interpolated (16) and modulated by a multivalued delta sigma modulator.
摘要:
Clock generating circuitry includes a frequency dividing circuit for dividing the frequency of an input clock by each of a plurality of predetermined frequency dividing ratios which differ from each other to generate a plurality of frequency-divided clocks such that a frequency-divided clock generated with the smallest frequency dividing ratio, i.e., a frequency-divided clock having the highest frequency, is slightly delayed against all of the other generated frequency-divided clocks. When changing the frequency of an output clock, a multiplexer switches from a previously selected one of the plurality of generated frequency-divided clocks to a desired clock in responsive to a control signal. The desired frequency-divided clock is then furnished as the output clock. Even when the plurality of frequency-divided clocks are not in phase with each other because of unit-to-unit variation when manufacturing the frequency dividing circuit, or due to changes in the operating conditions such as ambient temperature and voltages, the first clock pulse generated when the multiplexer performs the switching operation cannot have a shorter pulse width than pulses of the frequency-divided clock having the highest frequency.
摘要:
To allow an AP which performs operation based on a time of a system clock and another AP which performs operation based on a user-specified time to be executed concurrently in a data processing unit with only one system clock without having to change the time of the system clock, virtual system time setting means 5 receive a command or job start date and/or time from an input/output unit 2 and store it in a virtual system time storage area 4. In response to a system date acquisition function 6 or a system time acquisition function 7 from a command or a job, virtual system time converting means return either the date of the system clock when the date is not stored in the virtual system time storage area 4 or the date stored in the date storage area when the date is stored therein. The means also return either the time of the system clock when the time is not stored in the virtual system time storage area or the time of said system clock plus the time stored in said time storage area when the time is stored therein.
摘要:
An information processing apparatus includes an instruction memory, an instruction register, a plurality of function blocks, an instruction/state decoder, and a clock supply/stop circuit. The instruction memory stores instructions. An instruction is loaded from the instruction memory into the instruction register. The function blocks perform a basic operation required for execution of the instruction. The instruction/state decoder decodes the instruction read out from the instruction register, and also decodes a control signal used for notification of a state between the function blocks. The clock supply/stop circuit supplies a clock signal to a function block, of the plurality of function blocks, which is required for execution of the decoded instruction and needs to operate, on the basis of an output signal from the instruction/state decoder.
摘要:
A microcontroller integrated circuit incorporating a user configurable pulse width modulator. The pulse width modulator circuitry is configurable to be a single, for example 32-bit pulse width modulator, or a plurality of pulse width modulators each having a bit width that is divisible by the single 32-bit pulse width modulator (e.g., 2, 4, 8 or 16-bit pulse width modulators).
摘要:
An integrated circuit constructed for easy debug and emulation includes a function clock circuit and an operation circuit operating in synchronism with a function clock. A trace trigger circuit triggers trace operation upon detection of a predetermined condition within the operation circuit. A FIFO buffer receives the trace data which is exported via a trace port. The integrated circuit includes an oscillator clock circuit which may be synchronized with the function clock or a reference clock. The oscillator clock circuit operates in several modes selected by an externally writeable control register. The clock circuit synchronizes with the function clock signal or a reference clock signal as selected by the control register. Pre-scalers are employed in two paths to scale the oscillator clock frequency. The clock circuit also includes calibration and test modes selected by the control register.