公开(公告)号：US08305007B2

公开(公告)日：2012-11-06

申请号：US12504841

申请日：2009-07-17

Applicant: Bin Zhao

Inventor： Bin Zhao

IPC: G05F1/00

CPC classification number: H03M1/1235 ,  H05B33/0827

Abstract: An analog-to-digital converter (ADC) implements non-uniform conversion accuracy so as to allow for high conversion accuracy for a select narrower input range while also accommodating a wider overall input range and requiring fewer conversion bits compared to conventional ADCs. The ADC includes an ADC core that receives an input signal and outputs a first digital value having a first number of bits, the first digital value based on the input signal and an accuracy configuration of the ADC core. The ADC also includes an encoder to generate a second digital value have a second number of bits, greater than the first number of bits, based on the first digital value and the accuracy configuration of the ADC core. The ADC further includes an accuracy controller to adjust the accuracy configuration of the ADC core based on a relationship between the first digital value and at least one threshold.

Abstract translation: 模数转换器（ADC）实现了非均匀的转换精度，以便在选择更窄的输入范围内实现高转换精度，同时还适应更宽的整体输入范围，与传统ADC相比需要较少的转换位。 ADC包括ADC内核，其接收输入信号并输出​​具有第一数量位的第一数字值，基于输入信号的第一数字值和ADC内核的精度配置。 ADC还包括一个编码器，用于根据第一数字值和ADC内核的精度配置，产生具有大于第一位数的第二位数的第二数字值。 ADC还包括精度控制器，用于基于第一数字值与至少一个阈值之间的关系来调整ADC内核的精度配置。

公开(公告)号：US20120249094A1

公开(公告)日：2012-10-04

申请号：US13216522

申请日：2011-08-24

Applicant: Bin Zhao ,  Jack Cornish ,  Victor Lee

Inventor： Bin Zhao ,  Jack Cornish ,  Victor Lee

IPC: G05F1/10 ,  H02J4/00

CPC classification number: H02M3/00 ,  H02M2001/0003 ,  Y10T307/25

Abstract: In one general aspect, an apparatus can include a controller, and a power stage coupled to the controller and configured to be coupled to a power source. The power stage is configured to deliver an output voltage to a load module in response to the controller. The apparatus also includes a reference voltage circuit coupled to the controller and configured to be grounded to a first ground voltage different from a second ground voltage associated with the load module.

Abstract translation: 在一个一般方面，装置可以包括控制器和耦合到控制器并被配置为耦合到电源的功率级。 功率级被配置为响应于控制器将输出电压递送到负载模块。 该装置还包括耦合到控制器并被配置为接地到不同于与负载模块相关联的第二接地电压的第一接地电压的参考电压电路。

公开(公告)号：US20120207205A1

公开(公告)日：2012-08-16

申请号：US13025201

申请日：2011-02-11

Applicant: Bin Zhao ,  Jack W. Cornish ,  Andrew M. Kameya ,  Weizhuang W. Xin

Inventor： Bin Zhao ,  Jack W. Cornish ,  Andrew M. Kameya ,  Weizhuang W. Xin

IPC: H03K9/08

CPC classification number: H05B33/0827 ,  G09G3/3406 ,  G09G2320/064

Abstract: First information is received at a first pulse width modulation (PWM) module responsive to a chip select signal being asserted at a chip select input of a communication bus of the first PWM module during a first time. The first information is latched at a control register of the first PWM module in response to a first logic transition of the chip select signal. A first PWM signal is provided at a first output of the first PWM module beginning a predetermined amount of time after the first logic transition of the chip select signal, the first PWM signal generated by the first PWM module based upon the first information.

Abstract translation: 响应于在第一时间期间在第一PWM模块的通信总线的芯片选择输入端被断言的芯片选择信号，第一脉冲宽度调制（PWM）模块接收第一信息。 响应于芯片选择信号的第一逻辑转换，第一信息被锁存在第一PWM模块的控制寄存器中。 第一PWM信号设置在第一PWM模块的第一输出处，在芯片选择信号的第一逻辑转换，基于第一信息由第一PWM模块产生的第一PWM信号之后开始预定的时间量。

公开(公告)号：US08154878B2

公开(公告)日：2012-04-10

申请号：US12510782

申请日：2009-07-28

Applicant: Xiao-Zhou Wang ,  Zhen-Gang Ding ,  Bin Zhao ,  Lei Wang

Inventor： Xiao-Zhou Wang ,  Zhen-Gang Ding ,  Bin Zhao ,  Lei Wang

IPC: H05K5/00

CPC classification number: H01R12/7005 ,  G06K13/08

Abstract: An exemplary chip card holder used in a portable electronic device for holding a chip card is provided. The chip card holder includes a body member, a card receiving space disposed on the body member, an elastic piece and a releasing piece. The elastic piece is disposed at one end of the card receiving space and is configured for elastically resisting against the chip card to provide a pushing force to the chip card. The releasing piece is releasably disposed at the other end of the card receiving space opposite to the elastic piece and being configured to hold and release the chip card. The chip card locking device has simple structure and is easy to operate to lock or unlock the chip card.

Abstract translation: 提供了用于保持芯片卡的便携式电子设备中使用的示例性芯片卡保持器。 芯片卡座包括本体构件，设置在主体构件上的卡片容纳空间，弹性片和释放片。 弹性片设置在卡接收空间的一端，并且被配置为弹性抵抗芯片卡以向芯片卡提供推力。 释放片被可释放地设置在与弹性片相对的卡片接收空间的另一端，并被配置为保持和释放芯片卡。 芯片卡锁定装置结构简单，易于操作以锁定或解锁芯片卡。

公开(公告)号：US08035314B2

公开(公告)日：2011-10-11

申请号：US12363294

申请日：2009-01-30

Applicant: Bin Zhao

Inventor： Bin Zhao

IPC: H05B37/02

CPC classification number: H05B33/0815 ,  H05B33/0857

Abstract: Disclosed are example open channel detection techniques at a light emitting diode (LED) driver of an LED system. The LED driver does not enable its LED channels before normal operation so as to inhibit current flow through the LED channels during start-up. While the LED channels are disabled, the LED driver compares the voltages at the LED channel inputs with a predetermined voltage to determine whether an operational LED string of an associated LED panel is connected to the LED channel. In the event that an LED channel is determined to be an “open” channel, the LED driver further disables the LED channel for the following normal operational mode. Otherwise, if the LED channel is determined to be connected to an operational LED string, the LED driver enables the LED channel for the normal operational mode, during which the LED channel can be selectively activated for light output subject to display data for the LED panel.

Abstract translation: 公开了LED系统的发光二极管（LED）驱动器处的示例性开放通道检测技术。 LED驱动器在正常操作之前不能使能其LED通道，以便在启动期间禁止通过LED通道的电流。 当LED通道被禁用时，LED驱动器将LED通道输入端的电压与预定电压进行比较，以确定相关LED面板的工作LED串是否连接到LED通道。 在LED通道确定为“开路”通道的情况下，LED驱动器进一步禁用LED通道用于以下正常操作模式。 否则，如果LED通道被确定为连接到可操作的LED串，则LED驱动器使得LED通道能够进入正常操作模式，在此期间LED通道可以选择性地激活以进行LED输出的显示数据 。

公开(公告)号：US20110193605A1

公开(公告)日：2011-08-11

申请号：US12703249

申请日：2010-02-10

Applicant: Bin Zhao

Inventor： Bin Zhao

IPC: H03K3/017

CPC classification number: H05B33/0818 ,  G06F1/025 ,  Y02B20/346

Abstract: A pulse width modulation (PWM) signal generator generates a PWM signal with an adjustable PWM duty based on a programmable or otherwise adjustable value. In response to a change or update to this value, the PWM signal generator initiates a duty transition process that generates a series of groups of PWM cycles that gradually transition from the original duty to the new duty. Each group includes a corresponding set of a predetermined number of PWM cycles that is repeated one or more times over a predetermined duration for the group. Each set has a certain proportion of PWM cycles having the new duty to PWM cycles having the original duty, whereby the proportion increases for each successive group of the series. This gradual transition in the PWM signal from the original duty to the new duty effectively provides an effective higher duty resolution for the PWM signal generator during the duty transition.

Abstract translation: 脉冲宽度调制（PWM）信号发生器基于可编程或其他可调整的值产生具有可调PWM占空比的PWM信号。 响应于该值的更改或更新，PWM信号发生器启动占空比转换过程，该过程产生逐渐从原始占空比转换到新占空比的一系列PWM周期。 每个组包括在该组的预定持续时间内重复一次或多次的预定数量的PWM周期的相应组。 每组具有一定比例的PWM周期，其具有具有原始占空比的PWM周期的新占空比，由此该系列的每个连续组的比例增加。 在占空比过渡期间，PWM信号从原始占空比到新占空比的逐渐转换有效地为PWM信号发生器提供了更高的占空比分辨率。

公开(公告)号：US20110121761A1

公开(公告)日：2011-05-26

申请号：US12625818

申请日：2009-11-25

Applicant: Bin Zhao

Inventor： Bin Zhao

IPC: H05B43/00 ,  H03L7/07

CPC classification number: H05B33/0818 ,  H05B33/0827 ,  H05B33/0848

Abstract: A pulse width modulation (PWM) signal generator generates multiple output PWM signals from an input PWM signal. The output PWM signals are synchronized to synchronization events. Each output PWM signal has a duty ratio substantially equal to the duty ratio of the input PWM signal, and each output PWM signal has a fixed phase-shift in relation to the other output PWM signals. The PWM signal generator samples an input PWM cycle to determine sample parameters representative of its duty ratio. The sample parameters are then used to generate a corresponding output PWM cycle for each of the output PWM signals. In response to a synchronization event, the PWM signal generator prematurely terminates the current PWM cycle and initiates the next PWM cycle while ensuring that the portion of the current output PWM cycle completed by the leading output PWM signal up to the point of the premature termination is replicated for the corresponding output PWM cycles of the other non-leading output PWM signals.

Abstract translation: 脉宽调制（PWM）信号发生器从输入PWM信号产生多个输出PWM信号。 输出PWM信号与同步事件同步。 每个输出PWM信号的占空比基本上等于输入PWM信号的占空比，并且每个输出PWM信号相对于其它输出PWM信号具有固定的相移。 PWM信号发生器对输入PWM周期进行采样，以确定代表其占空比的采样参数。 然后使用采样参数为每个输出PWM信号产生相应的输出PWM周期。 响应于同步事件，PWM信号发生器过早地终止当前的PWM周期并启动下一个PWM周期，同时确保由引导输出PWM信号完成的电流输出PWM周期的部分直到提前终止点为止 复制其他非前置输出PWM信号的相应输出PWM周期。

公开(公告)号：US20110012519A1

公开(公告)日：2011-01-20

申请号：US12504841

申请日：2009-07-17

Applicant: Bin Zhao

Inventor： Bin Zhao

IPC: H05B37/02 ,  H03M1/10

CPC classification number: H03M1/1235 ,  H05B33/0827

Abstract: An analog-to-digital converter (ADC) implements non-uniform conversion accuracy so as to allow for high conversion accuracy for a select narrower input range while also accommodating a wider overall input range and requiring fewer conversion bits compared to conventional ADCs. The ADC includes an ADC core that receives an input signal and outputs a first digital value having a first number of bits, the first digital value based on the input signal and an accuracy configuration of the ADC core. The ADC also includes an encoder to generate a second digital value have a second number of bits, greater than the first number of bits, based on the first digital value and the accuracy configuration of the ADC core. The ADC further includes an accuracy controller to adjust the accuracy configuration of the ADC core based on a relationship between the first digital value and at least one threshold.

Abstract translation: 模数转换器（ADC）实现了非均匀的转换精度，以便在选择更窄的输入范围内实现高转换精度，同时还适应更宽的整体输入范围，与传统ADC相比需要较少的转换位。 ADC包括ADC内核，其接收输入信号并输出​​具有第一数量位的第一数字值，基于输入信号的第一数字值和ADC内核的精度配置。 ADC还包括一个编码器，用于根据第一数字值和ADC内核的精度配置，产生具有大于第一位数的第二位数的第二数字值。 ADC还包括精度控制器，用于基于第一数字值与至少一个阈值之间的关系来调整ADC内核的精度配置。

公开(公告)号：US20100191881A1

公开(公告)日：2010-07-29

申请号：US12358437

申请日：2009-01-23

Applicant: Marcin P. Tauter ,  Christine Teresa Munson ,  Lin Shi ,  Bin Zhao ,  Peter A. Cryer ,  George D. Watt ,  Vasken Torossian

Inventor： Marcin P. Tauter ,  Christine Teresa Munson ,  Lin Shi ,  Bin Zhao ,  Peter A. Cryer ,  George D. Watt ,  Vasken Torossian

IPC: G06F13/00

CPC classification number: G06Q10/06

Abstract: A method for reserving and provisioning IT resources comprises receiving, from a user, a request to reserve a desired configuration of IT resources. The desired configuration comprises one or more desired technical specifications and a desired reservation time having a start time and an end time. The method further comprises accessing an IT resource database to determine one or more of a plurality of resource pools that the user has access to. The one or more resource pools are consulted to determine if one or more IT resources matching the desired configuration are available. If the one or more IT resources matching the desired configuration are available, the one or more IT resources are reserved for the user and provided to the user at the start time.

Abstract translation: 用于保留和配置IT资源的方法包括从用户接收保留IT资源的期望配置的请求。 期望的配置包括一个或多个期望的技术规范和具有开始时间和结束时间的期望的预留时间。 该方法还包括访问IT资源数据库以确定用户具有访问权限的多个资源池中的一个或多个。 咨询一个或多个资源池以确定是否有可用与所需配置匹配的一个或多个IT资源。 如果符合所需配置的一个或多个IT资源可用，则一个或多个IT资源被保留给用户并且在开始时提供给用户。

公开(公告)号：US20100156315A1

公开(公告)日：2010-06-24

申请号：US12340985

申请日：2008-12-22

Applicant: Bin Zhao ,  Jack W. Cornish ,  Brian B. Horng ,  Andrew M. Kameya ,  Jan Krellner ,  Kenneth C. Kwok ,  Victor K. Lee ,  Weizhuang W. Xin

Inventor： Bin Zhao ,  Jack W. Cornish ,  Brian B. Horng ,  Andrew M. Kameya ,  Jan Krellner ,  Kenneth C. Kwok ,  Victor K. Lee ,  Weizhuang W. Xin

IPC: H05B41/36

CPC classification number: H05B33/0818 ,  H05B33/0827 ,  H05B33/0851

Abstract: Power management in a light emitting diode (LED) system having a plurality of LED strings is disclosed. A voltage source provides an output voltage to drive a plurality of LED strings. An LED driver implements a feedback mechanism to monitor the tail voltages of the active LED strings to identify the minimum tail voltage and adjust the output voltage of the voltage source based on the lowest tail voltage. A loop calibration module of the LED driver calibrates the feedback mechanism of the LED driver based on a relationship between a digital code value used to generate a particular output voltage and another digital code value generated based on the minimum tail voltage resulting from the particular output voltage.

Abstract translation: 公开了具有多个LED串的发光二极管（LED）系统中的电源管理。 电压源提供输出电压以驱动多个LED串。 LED驱动器实现反馈机制来监测有源LED串的尾部电压以识别最小尾电压，并且基于最低的尾部电压来调节电压源的输出电压。 LED驱动器的回路校准模块基于用于产生特定输出电压的数字代码值与基于由特定输出电压产生的最小尾部电压产生的另一数字代码值之间的关系来校准LED驱动器的反馈机制 。