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91.发明授权System, method and storage medium for providing fault detection and correction in a memory subsystem 有权用于在存储器子系统中提供故障检测和校正的系统，方法和存储介质公开(公告)号：US08140942B2
公开(公告)日：2012-03-20
申请号：US11851527
申请日：2007-09-07
申请人： Timothy J. Dell , Kevin C. Gower , Warren E. Maule
发明人： Timothy J. Dell , Kevin C. Gower , Warren E. Maule
IPC分类号： G11C29/00
CPC分类号： G11C5/04
摘要： A memory subsystem with a memory bus and a memory assembly. The memory bus includes multiple bitlanes. The memory assembly is in communication with the memory bus and includes instructions for receiving an error code correction (ECC) word in multiple packets via the memory bus. The ECC word includes data bits and ECC bits arranged into multiple multi-bit ECC symbols. Each of the ECC symbols is associated with one of the bitlanes on the memory bus. The memory assembly also includes instructions for utilizing one of the ECC symbols to perform error detection and correction for the bits in the ECC word received via the bitlane associated with the ECC symbol.
摘要翻译： 具有存储器总线和存储器组件的存储器子系统。 存储器总线包括多个位线。 存储器组件与存储器总线通信，并且包括用于经由存储器总线接收多个分组中的错误代码校正（ECC）字的指令。 ECC字包括排列成多个多位ECC符号的数据位和ECC位。 每个ECC符号与存储器总线上的位线之一相关联。 存储器组件还包括用于利用ECC符号之一对经由与ECC符号相关联的位层接收的ECC字中的比特进行错误检测和校正的指令。
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92.发明授权System for a combined error correction code and cyclic redundancy check code for a memory channel 有权用于存储器通道的组合纠错码和循环冗余校验码的系统公开(公告)号：US08140936B2
公开(公告)日：2012-03-20
申请号：US12018926
申请日：2008-01-24
申请人： Kevin C. Gower , Warren E. Maule
发明人： Kevin C. Gower , Warren E. Maule
IPC分类号： H03M13/00
CPC分类号： H03M13/09 , G06F11/1004
摘要： A memory system is provided that performs error correction at a memory device level. The memory system comprises a memory hub device integrated in the memory module and a link interface integrated in the memory hub device that provides a communication pathway between the memory hub device and an external memory controller. The link interface comprises first error correction logic integrated in the link interface that performs error correction operations on first data that is received from the external memory controller via a first memory channel to be transmitted to a set of memory devices. The first error correction logic generates a first error signal to the external memory controller in response to the first error correction logic detecting a first error in the first data. Link interface control logic integrated in the link interface controls the transmission of the first data to the set of memory devices.
摘要翻译： 提供了一种在存储器级别进行纠错的存储器系统。 存储器系统包括集成在存储器模块中的存储器集线器设备和集成在存储器集线器设备中的链路接口，其提供存储器集线器设备和外部存储器控制器之间的通信路径。 链路接口包括集成在链路接口中的第一纠错逻辑，其对经由要发送到一组存储器装置的第一存储器信道从外部存储器控制器接收到的第一数据执行纠错操作。 第一纠错逻辑响应于第一纠错逻辑检测第一数据中的第一误差，向外部存储器控制器产生第一误差信号。 链路接口控制逻辑集成在链路接口中，控制将第一个数据传输到一组存储器件。
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93.发明授权System to reduce latency by running a memory channel frequency fully asynchronous from a memory device frequency 失效通过运行内存通道频率与内存设备频率完全不同的系统来减少延迟公开(公告)号：US07925824B2
公开(公告)日：2011-04-12
申请号：US12019043
申请日：2008-01-24
IPC分类号： G06F12/00
CPC分类号： G06F13/4243
摘要： A memory system is provided that reduces latency by running a memory channel fully asynchronous from a memory device frequency. The memory system comprises a memory hub device integrated in a memory module. The memory hub device comprises a command queue that receives a memory access command from an external memory controller via a memory channel at a first operating frequency. The memory system also comprises a memory hub controller integrated in the memory hub device. The memory hub controller reads the memory access command from the command queue at a second operating frequency. By receiving the memory access command at the first operating frequency and reading the memory access command at the second operating frequency an asynchronous boundary is implemented. The first operating frequency is a maximum designed operating frequency of the memory channel and the first operating frequency is independent of the second operating frequency.
摘要翻译： 提供了一种通过从存储器件频率运行完全异步的存储器通道来减少延迟的存储器系统。 存储器系统包括集成在存储器模块中的存储器集线器设备。 存储器集线器设备包括命令队列，其经由存储器通道以第一工作频率从外部存储器控制器接收存储器访问命令。 存储器系统还包括集成在存储器集线器设备中的存储器集线器控制器。 存储器集线器控制器以第二工作频率从命令队列读取存储器访问命令。 通过以第一工作频率接收存储器访问命令并且以第二工作频率读取存储器访问命令，实现异步边界。 第一个工作频率是存储器通道的最大设计工作频率，第一个工作频率与第二个工作频率无关。
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公开(公告)号：US07890676B2
公开(公告)日：2011-02-15
申请号：US12185533
申请日：2008-08-04
CPC分类号： G06F13/1684 , G06F13/1673 , G06F13/1678 , Y02D10/14
摘要： Memory systems are disclosed that include a memory controller; an outbound link, the memory controller connected to the outbound link, the outbound link comprising a number of conductive pathways that conduct memory signals from the memory controller to memory buffer devices in a first memory layer; and at least two memory buffer devices in a first memory layer, each memory buffer device in the first memory layer connected to the outbound link to receive memory signals from the memory controller.
摘要翻译： 公开了包括存储器控制器的存储器系统; 出站链路，连接到出站链路的存储器控制器，出站链路包括将存储器信号从存储器控制器传送到第一存储器层中的存储器缓冲器设备的多个导电路径; 以及第一存储器层中的至少两个存储器缓冲器件，所述第一存储器层中的每个存储器缓冲器件连接到所述出站链路以从所述存储器控制器接收存储器信号。
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95.发明授权Buffered memory module with multiple memory device data interface ports supporting double the memory capacity 失效缓冲存储器模块具有多个存储器件数据接口端口，支持双倍的存储容量公开(公告)号：US07840748B2
公开(公告)日：2010-11-23
申请号：US11848318
申请日：2007-08-31
申请人： Kevin C. Gower , Warren E. Maule
发明人： Kevin C. Gower , Warren E. Maule
IPC分类号： G06F13/00
CPC分类号： G06F13/1668
摘要： A memory system is provided that enhances the memory bandwidth available through a memory module. The memory system includes a memory controller and at least one memory module coupled to the memory controller. In the memory systems, each memory module comprises at least one memory hub device integrated in the memory module. In the memory system, each memory hub device in the memory module comprises a first memory device data interface that communicates with a first set of memory devices and a second memory device data interface that communicates with a second set of memory devices. In the memory system, the first set of memory devices which are separate from the second set of memory devices are communicated with by the memory hub device via the separate first and second memory device data interfaces.
摘要翻译： 提供了一种存储器系统，其增强了通过存储器模块可用的存储器带宽。 存储器系统包括存储器控制器和耦合到存储器控制器的至少一个存储器模块。 在存储器系统中，每个存储器模块包括集成在存储器模块中的至少一个存储器集线器设备。 在存储器系统中，存储器模块中的每个存储器集线器设备包括与第一组存储器件通信的第一存储器件数据接口和与第二组存储器件通信的第二存储器件数据接口。 在存储器系统中，与第二组存储器设备分离的第一组存储器件通过存储器集线器设备经由单独的第一和第二存储器件数据接口进行通信。
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96.发明申请PROVIDING A VARIABLE FRAME FORMAT PROTOCOL IN A CASCADE INTERCONNECTED MEMORY SYSTEM 审中-公开在CASCADE INTERCONNECTED MEMORY SYSTEM中提供可变框架格式协议公开(公告)号：US20100005212A1
公开(公告)日：2010-01-07
申请号：US12166244
申请日：2008-07-01
IPC分类号： G06F13/28
CPC分类号： G06F13/4234
摘要： Systems and methods for providing a variable frame format protocol in a cascade interconnected memory system. The systems include a memory hub device that utilizes a first bus interface to communicate on a high-speed bus. The hub device also includes frame decode logic for translating variable format frames received via the first bus interface into memory device commands and data. The translating includes identifying write data headers and associated write data for self-registering write to data buffer commands.
摘要翻译： 用于在级联互连存储器系统中提供可变帧格式协议的系统和方法。 这些系统包括利用第一总线接口在高速总线上通信的存储器集线器设备。 集线器设备还包括用于将经由第一总线接口接收的可变格式帧转换为存储器设备命令和数据的帧解码逻辑。 翻译包括识别写数据标题和相关联的写入数据，用于自写入对数据缓冲器命令的写入。
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97.发明授权Systems and methods for providing distributed technology independent memory controllers 失效提供分布式技术独立存储器控制器的系统和方法公开(公告)号：US07594055B2
公开(公告)日：2009-09-22
申请号：US11420034
申请日：2006-05-24
IPC分类号： G06F13/14
CPC分类号： G06F13/4243 , G06F13/4247
摘要： Systems and methods for providing distributed technology independent memory controllers. Systems include a computer memory system for storing and retrieving data. The system includes a memory bus, a main memory controller, one or more memory devices characterized by memory device protocols and signaling requirements, and one or more memory hub devices. The main memory controller is in communication with the memory bus for generating, receiving, and responding to memory access requests. The hub devices are in communication with the memory bus and with the memory devices for controlling the memory devices responsively to the memory access requests received from the main memory controller and for responding to the main memory controller with state or memory data. The main memory controller and the hub devices communicate via the memory bus in messages in a message format and protocol for indicating memory read, memory write, memory system power management and control that is independent of the memory device protocols and signaling requirements.
摘要翻译： 提供分布式技术独立存储器控制器的系统和方法。 系统包括用于存储和检索数据的计算机存储器系统。 该系统包括存储器总线，主存储器控制器，以存储器件协议和信令要求为特征的一个或多个存储器件，以及一个或多个存储器集线器设备。 主存储器控制器与存储器总线通信，用于生成，接收和响应存储器访问请求。 集线器设备与存储器总线和存储器设备通信，用于响应于从主存储器控制器接收的存储器访问请求来控制存储器件并且用状态或存储器数据对主存储器控制器进行响应。 主存储器控制器和集线器设备通过消息中的消息格式和协议通过存储器总线进行通信，用于指示独立于存储器件协议和信令要求的存储器读取，存储器写入，存储器系统电源管理和控制。
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98.发明申请System and Method to Use Cache that is Embedded in a Memory Hub to Replace Failed Memory Cells in a Memory Subsystem 有权使用嵌入在内存中心中的缓存来替换内存子系统中的故障内存单元的系统和方法公开(公告)号：US20090193290A1
公开(公告)日：2009-07-30
申请号：US12019141
申请日：2008-01-24
IPC分类号： G06F11/20
CPC分类号： G06F12/0802 , G06F11/1666 , G06F11/20 , G11C5/04 , G11C29/808
摘要： A memory system, data processing system, and method are provided for using cache that is embedded in a memory hub device to replace failed memory cells. A memory module comprises an integrated memory hub device. The memory hub device comprises an integrated memory device data interface that communicates with a set of memory devices coupled to the memory hub device and a cache integrated in the memory hub device. The memory hub device also comprises an integrated memory hub controller that controls the data that is read or written by the memory device data interface to the cache based on a determination whether one or more memory cells within the set of memory devices has failed.
摘要翻译： 提供了一种存储系统，数据处理系统和方法，用于使用嵌入在存储器集线器设备中的高速缓存来代替故障存储器单元。 存储器模块包括集成存储器集线器设备。 存储器集线器设备包括与耦合到存储器集线器设备的一组存储器设备和集成在存储器集线器设备中的高速缓存器通信的集成存储器设备数据接口。 存储器集线器设备还包括集成存储器集线器控制器，其基于确定存储器装置集合内的一个或多个存储器单元是否已经失败来控制由存储器件数据接口读取或写入高速缓存的数据。
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99.发明申请System to Increase the Overall Bandwidth of a Memory Channel By Allowing the Memory Channel to Operate at a Frequency Independent from a Memory Device Frequency 失效通过允许存储器通道以独立于存储器件频率的频率操作来增加存储器通道的总体带宽的系统公开(公告)号：US20090193201A1
公开(公告)日：2009-07-30
申请号：US12019095
申请日：2008-01-24
IPC分类号： G06F12/00
CPC分类号： G06F13/1689
摘要： A memory system is provided that increases the overall bandwidth of a memory channel by operating the memory channel at a independent frequency. The memory system comprises a memory hub device integrated in a memory module. The memory hub device comprises a command queue that receives a memory access command from an external memory controller via a memory channel at a first operating frequency. The memory system also comprises a memory hub controller integrated in the memory hub device. The memory hub controller reads the memory access command from the command queue at a second operating frequency. By receiving the memory access command at the first operating frequency and reading the memory access command at the second operating frequency an asynchronous boundary is implemented. Using the asynchronous boundary, the memory channel operates at a maximum designed operating bandwidth, which is independent of the second operating frequency.
摘要翻译： 提供了一种存储器系统，其通过以独立频率操作存储器通道来增加存储器通道的总体带宽。 存储器系统包括集成在存储器模块中的存储器集线器设备。 存储器集线器设备包括命令队列，其经由存储器通道以第一工作频率从外部存储器控制器接收存储器访问命令。 存储器系统还包括集成在存储器集线器设备中的存储器集线器控制器。 存储器集线器控制器以第二工作频率从命令队列读取存储器访问命令。 通过以第一工作频率接收存储器访问命令并且以第二工作频率读取存储器访问命令，实现异步边界。 使用异步边界，存储通道以最大设计的工作带宽运行，独立于第二个工作频率。
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100.发明申请公开(公告)号：US20090193200A1
公开(公告)日：2009-07-30
申请号：US12019071
申请日：2008-01-24
IPC分类号： G06F12/00
CPC分类号： G06F13/4243
摘要： A memory system is provided that implements an asynchronous boundary in a memory module. The memory system comprises a memory hub device integrated in a memory module. The memory system also comprises a set of memory devices coupled to the memory hub device. The memory hub device comprises a command queue that receives a memory access command from an external memory controller via a memory channel at a first operating frequency. The memory system further comprises a memory hub controller integrated in the memory hub device. The memory hub controller reads the memory access command from the command queue at a second operating frequency. By receiving the memory access command at the first operating frequency and reading the memory access command at the second operating frequency an asynchronous boundary is implemented within the memory hub device of the memory module.
摘要翻译： 提供了一种在存储器模块中实现异步边界的存储器系统。 存储器系统包括集成在存储器模块中的存储器集线器设备。 存储器系统还包括耦合到存储器集线器设备的一组存储器件。 存储器集线器设备包括命令队列，其经由存储器通道以第一工作频率从外部存储器控制器接收存储器访问命令。 存储器系统还包括集成在存储器集线器设备中的存储器集线器控制器。 存储器集线器控制器以第二工作频率从命令队列读取存储器访问命令。 通过以第一工作频率接收存储器访问命令并且以第二工作频率读取存储器访问命令，在存储器模块的存储器集线器设备内实现异步边界。
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