公开(公告)号：US10971214B2

公开(公告)日：2021-04-06

申请号：US16827044

申请日：2020-03-23

Applicant: Micron Technology, Inc.

Inventor： Harish N. Venkata ,  Daniel B. Penney

IPC: G11C11/00 ,  G11C11/4091 ,  G11C11/4093 ,  G11C11/408 ,  G11C7/02

Abstract: The present disclosure includes apparatuses and methods related to performing logic operations. An example apparatus comprises sensing circuitry including a sense amplifier and a compute component. A controller is coupled to the sensing circuitry and is configured to cause storing of a first operand in a first compute component storage location, transfer of the first operand to a second compute component storage location, and performance of a logical operation between the first operand in the second compute component storage location and a second operand sensed by the sense amplifier.

公开(公告)号：US10929283B2

公开(公告)日：2021-02-23

申请号：US16543810

申请日：2019-08-19

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  Gary L. Howe

IPC: G06F12/02 ,  G06F12/0855 ,  G06F13/16

Abstract: The present disclosure includes apparatuses and methods related to shifting data. An example apparatus comprises a cache coupled to an array of memory cells and a controller. The controller is configured to perform a first operation beginning at a first address to transfer data from the array of memory cells to the cache, and perform a second operation concurrently with the first operation, the second operation beginning at a second address.

公开(公告)号：US20210020262A1

公开(公告)日：2021-01-21

申请号：US17060403

申请日：2020-10-01

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Daniel B. Penney ,  Jason M. Brown

IPC: G11C29/00 ,  G11C11/406 ,  G11C11/408

Abstract: Addresses of accessed word lines are stored. Data related to victim word lines associated with the accessed word line are also stored. The victim word lines may have data stored in relation to multiple accessed word lines. The data related to the victim word lines is adjusted when the victim word line is refreshed during a targeted refresh operation or an auto-refresh operation. The data related to the victim word lines is adjusted when the victim word line is accessed during a memory access operation.

公开(公告)号：US10885968B2

公开(公告)日：2021-01-05

申请号：US16457403

申请日：2019-06-28

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney

IPC: G11C11/4076 ,  G11C11/4096 ,  G11C7/10 ,  G11C7/22

Abstract: Devices and methods include receiving write command at a command interface of the semiconductor device to write data to memory. An external data strobe is received at a data strobe pin of the semiconductor device. The received external data strobe is divided into multiple phases using phase division circuitry to divide the data strobe into multiple phases to be used in writing the data to the memory.

公开(公告)号：US10600473B2

公开(公告)日：2020-03-24

申请号：US16549554

申请日：2019-08-23

Applicant: Micron Technology, Inc.

Inventor： Harish N. Venkata ,  Daniel B. Penney

IPC: G11C7/02 ,  G11C11/4091 ,  G11C11/408 ,  G11C11/4093

Abstract: The present disclosure includes apparatuses and methods related to performing logic operations. An example apparatus comprises sensing circuitry including a sense amplifier and a compute component. A controller is coupled to the sensing circuitry and is configured to cause storing of a first operand in a first compute component storage location, transfer of the first operand to a second compute component storage location, and performance of a logical operation between the first operand in the second compute component storage location and a second operand sensed by the sense amplifier.

公开(公告)号：US10418090B1

公开(公告)日：2019-09-17

申请号：US16014539

申请日：2018-06-21

Applicant: Micron Technology, Inc.

Inventor： Ming-Bo Liu ,  Daniel B. Penney

IPC: G11C7/22 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096

Abstract: Systems and methods include capture circuitry configured to capture a write signal from a host device using a data strobe signal from the host device and to output one or more indications of capture of the write signal. Calculation circuitry is configured to receive the data strobe signal, receive the one or more indications of capture, and determine a delay between a first edge of the data strobe signal and receipt of the one or more indications of capture. The systems and methods also include transmission and control circuitry configured to launch subsequent write signals at a time based at least in part on the delay.

公开(公告)号：US20190259431A1

公开(公告)日：2019-08-22

申请号：US16051189

申请日：2018-07-31

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  Liang Chen ,  David R. Brown

IPC: G11C7/10 ,  H04L25/03 ,  G11C7/22

Abstract: Methods and devices include an input buffer configured to receive data. Decision feedback equalizer (DFE) circuitry includes a DFE configured to interpret levels of the data from the input buffer and a DFE buffer that stores previous values to control the DFE based on the previous values. Moreover, the DFE circuitry also includes reset circuitry configured to reset the DFE buffer to an initial state. Furthermore, the DFE circuitry includes suppression circuitry configured to suppress resets using the reset circuitry for an interval between write operations to the memory device.

公开(公告)号：US10387046B2

公开(公告)日：2019-08-20

申请号：US15189900

申请日：2016-06-22

Applicant: Micron Technology, Inc.

Inventor： Thanh K. Mai ,  Gary L. Howe ,  Daniel B. Penney

IPC: G11C8/00 ,  G06F3/06 ,  G06F13/16

Abstract: The present disclosure includes apparatuses and methods to transfer data between banks of memory cells. An example includes a plurality of banks of memory cells and a controller coupled to the plurality of subarrays configured to cause transfer of data between the plurality of banks of memory cells via internal data path operations.

公开(公告)号：US20190244645A1

公开(公告)日：2019-08-08

申请号：US15891353

申请日：2018-02-07

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  Liang Chen

IPC: G11C8/18 ,  G11C7/10 ,  G06F13/16 ,  G06F13/42 ,  G11C29/50 ,  G06F5/06

Abstract: Memory devices and methods include receiving data at an input buffer and outputting serial data. The serial shift data is passed toward a serial shift register that shifts its stored data into a data write bus in a parallel format. Serial shift register loading circuitry controls loading of a serial shift register. The serial shift register loading circuitry is configured to receive a data strobe signal and provide the data strobe to the serial shift register to cause the serial shift register to shift in the serial data during a write operation. The serial register loading circuitry includes gating circuitry that is configured to cutoff provision of the data strobe from the serial register loading circuitry based at least in part on a load signal that indicates that the data write bus has been loaded with the serial data in a parallel format.

公开(公告)号：US20190189183A1

公开(公告)日：2019-06-20

申请号：US15845874

申请日：2017-12-18

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney

IPC: G11C11/4076 ,  G11C11/4096

CPC classification number: G11C11/4076 ,  G11C7/1078 ,  G11C7/109 ,  G11C11/4096

Abstract: Devices and methods include receiving write command at a command interface of the semiconductor device to write data to memory. An external data strobe is received at a data strobe pin of the semiconductor device. The received external data strobe is divided into multiple phases using phase division circuitry to divide the data strobe into multiple phases to be used in writing the data to the memory.