公开(公告)号：US11699476B2

公开(公告)日：2023-07-11

申请号：US17375817

申请日：2021-07-14

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jason M. Brown ,  Daniel B. Penney

IPC: G11C11/00 ,  G11C11/406 ,  G11C11/408

CPC classification number: G11C11/406 ,  G11C11/4087

Abstract: An apparatus may include multiple memory devices. Each memory device may include multiple memory banks. Addresses of accessed word lines for a particular portion of memory and the number of times those word lines are accessed may be tracked by each memory device. When a memory device determines that an accessed word line is an aggressor word line, the memory device alerts other memory devices of the apparatus. The memory devices may then perform targeted refresh operations on victim word lines of the aggressor word line.

公开(公告)号：US11532346B2

公开(公告)日：2022-12-20

申请号：US16886284

申请日：2020-05-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jason M. Brown ,  Daniel B. Penney

IPC: G11C11/40 ,  G11C11/406 ,  G11C16/34 ,  G11C7/10 ,  G06F11/30 ,  G11C11/4076 ,  G11C7/00

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for scheduling targeted refreshes in a memory device. Memory cells in a memory device may be volatile and may need to be periodically refreshed as part of an auto-refresh operation. In addition, certain rows may experience faster degradation, and may need to undergo targeted refresh operations, where a specific targeted refresh address is provided and refreshed. The rate at which targeted refresh operations need to occur may be based on the rate at which memory cells are accessed. The memory device may monitor accesses to a bank of the memory, and may use a count of the accesses to determine if an auto-refresh address or a targeted refresh address will be refreshed.

公开(公告)号：US11513945B2

公开(公告)日：2022-11-29

申请号：US17181718

申请日：2021-02-22

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  Gary L. Howe

IPC: G06F12/02 ,  G06F12/0855 ,  G06F13/16

Abstract: The present disclosure includes apparatuses and methods related to shifting data. An example apparatus comprises a cache coupled to an array of memory cells and a controller. The controller is configured to perform a first operation beginning at a first address to transfer data from the array of memory cells to the cache, and perform a second operation concurrently with the first operation, the second operation beginning at a second address.

公开(公告)号：US11315622B2

公开(公告)日：2022-04-26

申请号：US16834144

申请日：2020-03-30

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  Parthasarathy Gajapathy ,  Brian J. Ladner

IPC: G11C11/4076 ,  H03K3/037 ,  G11C11/4091 ,  G11C7/10 ,  G11C11/4093

Abstract: A multi-phase clock generator has a set of transistors, a first latch, and a second latch. The set of transistors may be arranged in a sense amplifier latch architecture, in which the set of transistors include a first inverter and a second inverter. The first inverter may provide a first phase data strobe signal and the second inverter may provide a second phase data strobe signal. The first latch and the second latch are coupled to the set of transistors. The set of transistors may receive a first portion of current at the first inverter and a second portion of current at the second inverter. The set of transistors may amplify the first portion of current in response to the first portion being greater than the second portion. The set of transistors may also drive the first phase data strobe signal using the amplified first portion.

公开(公告)号：US20210407583A1

公开(公告)日：2021-12-30

申请号：US17470883

申请日：2021-09-09

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  Jason M. Brown ,  Nathaniel J. Meier ,  Timothy B. Cowles ,  Jiyun Li

IPC: G11C11/406 ,  G11C11/408

Abstract: The address of victim rows may be determined based on rows that are accessed in a memory. The victim addresses may be stored and associated with a count for every time a victim row is “victimized.” When the count for a victim row reaches a threshold, the victim row may be refreshed to preserve data stored in the row. After the victim row has been refreshed, the count may be reset. When a victim row is accessed, the count may also be reset. The counts may be adjusted for closer victim rows (e.g., +/−1) at a faster rate than counts for more distant victim rows (e.g., +/−2). This may cause closer victim rows to be refreshed at a higher rate than more distant victim rows.

公开(公告)号：US20210343324A1

公开(公告)日：2021-11-04

申请号：US17375817

申请日：2021-07-14

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jason M. Brown ,  Daniel B. Penney

IPC: G11C11/406 ,  G11C11/408

Abstract: An apparatus may include multiple memory devices. Each memory device may include multiple memory banks. Addresses of accessed word lines for a particular portion of memory and the number of times those word lines are accessed may be tracked by each memory device. When a memory device determines that an accessed word line is an aggressor word line, the memory device alerts other memory devices of the apparatus. The memory devices may then perform targeted refresh operations on victim word lines of the aggressor word line.

公开(公告)号：US11144241B2

公开(公告)日：2021-10-12

申请号：US16534846

申请日：2019-08-07

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  Liang Chen

IPC: G06F3/06 ,  G11C11/40 ,  G11C11/4096 ,  G11C11/408 ,  G11C11/4076

Abstract: A host device and memory device function together to perform internal write leveling of a data strobe with a write command within the memory device. The memory device includes a command interface configured to receive write commands from the host device. The memory device also includes an input-output interface configured to receive the data strobe from the host device. The memory device also includes internal write circuitry configured to launch an internal write signal based at least in part on the write commands. The launch of the internal write signal is based at least in part on an indication from the host device that indicates when to launch the internal write signal relative to a cas write latency (CWL) for the memory device.

公开(公告)号：US20210304808A1

公开(公告)日：2021-09-30

申请号：US16834144

申请日：2020-03-30

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  Parthasarathy Gajapathy ,  Brian J. Ladner

IPC: G11C11/4076 ,  G11C11/4091 ,  H03K3/037

Abstract: A multi-phase clock generator has a set of transistors, a first latch, and a second latch. The set of transistors may be arranged in a sense amplifier latch architecture, in which the set of transistors include a first inverter and a second inverter. The first inverter may provide a first phase data strobe signal and the second inverter may provide a second phase data strobe signal. The first latch and the second latch are coupled to the set of transistors. The set of transistors may receive a first portion of current at the first inverter and a second portion of current at the second inverter. The set of transistors may amplify the first portion of current in response to the first portion being greater than the second portion. The set of transistors may also drive the first phase data strobe signal using the amplified first portion.

公开(公告)号：US10825494B2

公开(公告)日：2020-11-03

申请号：US16683018

申请日：2019-11-13

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  Liang Chen ,  David R. Brown

IPC: G11C7/10 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4093 ,  G11C8/18 ,  G11C8/10 ,  G11C11/4096 ,  H04L25/03 ,  G06F13/18 ,  G11C11/4074

Abstract: Methods and devices include an input buffer configured to receive data. Decision feedback equalizer (DFE) circuitry includes a DFE configured to interpret levels of the data from the input buffer and a DFE buffer that stores previous values to control the DFE based on the previous values. Moreover, the DFE circuitry also includes reset circuitry configured to reset the DFE buffer to an initial state. Furthermore, the DFE circuitry includes suppression circuitry configured to suppress resets using the reset circuitry for an interval between write operations to the memory device.

公开(公告)号：US10789996B2

公开(公告)日：2020-09-29

申请号：US16360685

申请日：2019-03-21

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  Harish N. Venkata ,  Guy S. Perry

IPC: G11C7/10 ,  G11C11/4096 ,  G11C11/4091

Abstract: The present disclosure includes apparatuses and methods related to shifting data. An example apparatus comprises sensing circuitry including a sense amplifier and a compute component having a first storage location and a second storage location associated therewith. A controller is coupled to the sensing circuitry. The controller is configured to control an amount of power associated with shifting a data value stored in the first storage location to the second storage location by applying a charge sharing operation.