公开(公告)号：US11537861B2

公开(公告)日：2022-12-27

申请号：US16909632

申请日：2020-06-23

Applicant: Micron Technology, Inc.

Inventor： Dmitri Yudanov ,  Sean S. Eilert ,  Hernan A. Castro ,  William A. Melton

IPC: G06N3/00 ,  G06N3/063 ,  G06F3/06 ,  G11C11/54 ,  H03M1/46 ,  G11C7/06 ,  G11C8/08 ,  G06N3/04

Abstract: Methods, apparatuses, and systems for in-or near-memory processing are described. Bits of a first number may be stored on a number of memory elements, wherein each memory element of the number of memory elements intersects a bit line and a word line of a number of word lines. A number of signals corresponding to bits of a second number may be driven on the number of word lines to generate a number of output signals. A value equal to a product of the first number and the second number may be generated based on the number of output signals.

公开(公告)号：US11438414B2

公开(公告)日：2022-09-06

申请号：US16424411

申请日：2019-05-28

Applicant: Micron Technology, Inc.

Inventor： Dmitri Yudanov ,  Ameen D. Akel ,  Samuel E. Bradshaw ,  Kenneth Marion Curewitz ,  Sean Stephen Eilert

IPC: G06F15/16 ,  H04L67/1097 ,  G06F12/1027 ,  G06F12/1009 ,  H04L67/51 ,  G06F12/02

Abstract: Systems, methods and apparatuses to provide memory as a service are described. For example, a borrower device is configured to: communicate with a lender device; borrow an amount of memory from the lender device; expand memory capacity of the borrower device for applications running on the borrower device, using at least the local memory of the borrower device and the amount of memory borrowed from the lender device; and service accesses by the applications to memory via communication link between the borrower device and the lender device.

公开(公告)号：US20220197814A1

公开(公告)日：2022-06-23

申请号：US17132537

申请日：2020-12-23

Applicant: Micron Technology, Inc.

Inventor： Dmitri Yudanov

IPC: G06F12/0893

Abstract: The disclosed embodiments relate to per-process configuration caches in storage devices. A method is disclosed comprising initiating a new process, the new process associated with a process context; configuring a region in a memory device, the region associated with the process context, wherein the configuring comprises setting one or more cache parameters that modify operation of the memory device; and mapping the process context to the region of the memory device

公开(公告)号：US11334387B2

公开(公告)日：2022-05-17

申请号：US16424413

申请日：2019-05-28

Applicant: Micron Technology, Inc.

Inventor： Sean Stephen Eilert ,  Ameen D. Akel ,  Samuel E. Bradshaw ,  Kenneth Marion Curewitz ,  Dmitri Yudanov

IPC: G06F9/50 ,  G06F12/1009 ,  G06F12/02 ,  H04L41/0896 ,  G06F13/16 ,  G06F12/08 ,  G06F12/1072 ,  G06F12/1036 ,  G06F12/126

Abstract: Systems, methods and apparatuses to throttle network communications for memory as a service are described. For example, a computing device can borrow an amount of random access memory of the lender device over a communication connection between the lender device and the computing device. The computing device can allocate virtual memory to applications running in the computing device, and configure at least a portion of the virtual memory to be hosted on the amount of memory loaned by the lender device to the computing device. The computing device can throttle data communications used by memory regions in accessing the amount of memory over the communication connection according to the criticality levels of the contents stored in the memory regions.

公开(公告)号：US11256624B2

公开(公告)日：2022-02-22

申请号：US16424421

申请日：2019-05-28

Applicant: Micron Technology, inc.

Inventor： Kenneth Marion Curewitz ,  Ameen D. Akel ,  Samuel E. Bradshaw ,  Sean Stephen Eilert ,  Dmitri Yudanov

IPC: G06F12/00 ,  G06F12/0837 ,  G06F12/1027 ,  G06F11/14 ,  G06F9/38 ,  G06F12/1009 ,  G06F13/00 ,  G06F13/28 ,  G06N3/02

Abstract: Systems, methods and apparatuses to intelligently migrate content involving borrowed memory are described. For example, after the prediction of a time period during which a network connection between computing devices having borrowed memory degrades, the computing devices can make a migration decision for content of a virtual memory address region, based at least in part on a predicted usage of content, a scheduled operation, a predicted operation, a battery level, etc. The migration decision can be made based on a memory usage history, a battery usage history, a location history, etc. using an artificial neural network; and the content migration can be performed by remapping virtual memory regions in the memory maps of the computing devices.

公开(公告)号：US20220027285A1

公开(公告)日：2022-01-27

申请号：US17496661

申请日：2021-10-07

Applicant: Micron Technology, Inc.

Inventor： Dmitri Yudanov ,  Ameen D. Akel ,  Samuel E. Bradshaw ,  Kenneth Marion Curewitz ,  Sean Stephen Eilert

IPC: G06F12/1009 ,  G06F12/1027 ,  G06N5/04 ,  H04L29/08 ,  H04W8/26

Abstract: Systems, methods and apparatuses of fine grain data migration in using Memory as a Service (MaaS) are described. For example, a memory status map can be used to identify the cache availability of sub-regions (e.g., cache lines) of a borrowed memory region (e.g., a borrowed remote memory page). Before accessing a virtual memory address in a sub-region, the memory status map is checked. If the sub-region has cache availability in the local memory, the memory management unit uses a physical memory address converted from the virtual memory address to make memory access. Otherwise, the sub-region is cached from the borrowed memory region to the local memory, before the physical memory address is used.

公开(公告)号：US20210391004A1

公开(公告)日：2021-12-16

申请号：US16902685

申请日：2020-06-16

Applicant: Micron Technology, Inc.

Inventor： Dmitri Yudanov

IPC: G11C13/00 ,  G06F16/2458

Abstract: Systems and methods for performing a pattern matching operation in a memory device are disclosed. The memory device may include a controller and memory arrays where the memory arrays store different patterns along bit lines. An input pattern is applied to the memory array(s) to determine whether the pattern is stored in the memory device. Word lines may be activated in series or in parallel to search for patterns within the memory array. The memory array may include memory cells that store binary digits, discrete values or analog values.

公开(公告)号：US11126548B1

公开(公告)日：2021-09-21

申请号：US16824618

申请日：2020-03-19

Applicant: Micron Technology, Inc.

Inventor： Dmitri Yudanov

IPC: G06F12/06 ,  G06F12/0877 ,  G11C11/4091 ,  G11C11/4094 ,  G06F13/16

Abstract: An apparatus having a memory array. The memory array having a first section and a second section. The first section of the memory array including a first sub-array of memory cells made up of a first type of memory. The second section of the memory array including a second sub-array of memory cells made up of the first type of memory with a configuration to each memory cell of the second sub-array that is different from the configuration to each cell of the first sub-array. Alternatively, the section can include memory cells made up of a second type of memory that is different from the first type of memory. Either way, the second type of memory or the differently configured first type of memory has memory cells in the second sub-array having less memory latency than each memory cell of the first type of memory in the first sub-array.

公开(公告)号：US20210182220A1

公开(公告)日：2021-06-17

申请号：US16713989

申请日：2019-12-13

Applicant: Micron Technology, Inc.

Inventor： Dmitri Yudanov

IPC: G06F13/16 ,  G06F13/40

Abstract: A memory module having a plurality of memory chips, at least one controller (e.g., a central processing unit or special-purpose controller), and at least one interface device configured to communicate input and output data for the memory module. The input and output data bypasses at least one processor (e.g., a central processing unit) of a computing device in which the memory module is installed. And, the at least one interface device can be configured to communicate the input and output data to at least one other memory module in the computing device. Also, the memory module can be one module in a plurality of memory modules of a memory module system.

公开(公告)号：US20210157646A1

公开(公告)日：2021-05-27

申请号：US16694371

申请日：2019-11-25

Applicant: Micron Technology, Inc.

Inventor： Dmitri Yudanov ,  Samuel E. Bradshaw

IPC: G06F9/50 ,  G06F9/451 ,  G06F13/16

Abstract: Enhancement or reduction of page migration can include operations that include scoring, in a computing device, each executable of at least a first group and a second group of executables in the computing device. The executables can be related to user interface elements of applications and associated with pages of memory in the computing device. For each executable, the scoring can be based at least partly on an amount of user interface elements using the executable. The first group can be located at first pages of the memory, and the second group can be located at second pages. When the scoring of the executables in the first group is higher than the scoring of the executables in the second group, the operations can include allocating or migrating the first pages to a first type of memory, and allocating or migrating the second pages to a second type of memory.