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97 条记录 (耗时 0.022 秒)

    Excitation system for synchronous machine
    91.
    发明申请
    Excitation system for synchronous machine 有权
    同步电机励磁系统

    公开(公告)号：US20070145938A1

    公开(公告)日：2007-06-28

    申请号：US11647148

    申请日：2006-12-29

    申请人： Yoichi Kato ,  Satoshi Kitamura

    发明人： Yoichi Kato ,  Satoshi Kitamura

    IPC分类号： H02P1/46

    CPC分类号： H03K17/725 ,  H02P25/024 ,  H02P27/16 ,  H03K17/125

    摘要： A synchronous machine regulator is provided to simplify an adjustment work of current distribution to thyristors, the synchronous machine regulator having a circuit board 32 mounting a gate drive circuit 33 for supplying a gate pulse to each of thyristor bridges constituting a plurality of thyristor rectifiers 44 connected in parallel and supplying excitation current to a field winding 2 of a synchronous machine 1, and phase control means 34 for controlling a phase angle of each gate pulse to be supplied to each thyristor, wherein the current distribution to thyristors is controlled by the phase control means 34.

    摘要翻译： 提供同步电机调节器以简化对晶闸管的电流分配的调整工作，同步电机调节器具有安装栅极驱动电路33的电路板32，栅极驱动电路33用于向构成连接的多个晶闸管整流器44的晶闸管桥供应栅极脉冲 并联并将励磁电流提供给同步电机1的励磁绕组2，以及相位控制装置34，用于控制要提供给每个晶闸管的每个栅极脉冲的相位角，其中通过相位控制来控制对晶闸管的电流分配 意味着34。

    Semiconductor device with circuit for phasing internal clock signal
    95.
    发明授权
    Semiconductor device with circuit for phasing internal clock signal 有权
    具有用于定时内部时钟信号的电路的半导体器件

    公开(公告)号：US06178123B1

    公开(公告)日：2001-01-23

    申请号：US09377904

    申请日：1999-08-20

    申请人： Yoichi Kato ,  Tsukasa Ooishi

    发明人： Yoichi Kato ,  Tsukasa Ooishi

    IPC分类号： G11C700

    CPC分类号： G11C7/222 ,  G11C7/22 ,  H03K5/131 ,  H03L7/0814 ,  H03L7/10

    摘要： An initial delay control data decision circuit detects to which portion of a variable delay circuit a pulse signal of an external clock signal of one cycle is propagated for a predetermined period of time, to determine an initial value for delay control data. Depending on the initial value for delay control data, a delay locked loop circuit configured of the variable delay circuit, a phase comparator circuit, a shift logic circuit, a delay control data holding circuit, a variable constant current circuit and a voltage generating circuit controls phasing of internal and external clock signals.

    摘要翻译： 初始延迟控制数据判定电路检测一个周期的外部时钟信号的脉冲信号在可变延迟电路的哪个部分传播预定的时间段，以确定延迟控制数据的初始值。 根据延迟控制数据的初始值，由可变延迟电路，相位比较器电路，移位逻辑电路，延迟控制数据保持电路，可变恒流电路和电压产生电路控制构成的延迟锁定环路电路 内部和外部时钟信号的定相。

    Synchronous semiconductor memory device capable of rapidly, highly precisely matching internal clock phase to external clock phase
    96.
    发明授权
    Synchronous semiconductor memory device capable of rapidly, highly precisely matching internal clock phase to external clock phase 有权
    同步半导体存储器件能够快速，高度精确地匹配内部时钟相位与外部时钟相位

    公开(公告)号：US5995441A

    公开(公告)日：1999-11-30

    申请号：US170223

    申请日：1998-10-13

    申请人： Yoichi Kato ,  Tsukasa Ooishi

    发明人： Yoichi Kato ,  Tsukasa Ooishi

    IPC分类号： G11C11/413 ,  G11C7/22 ,  G11C11/407 ,  G11C11/4076 ,  H03K5/13 ,  H03L7/081 ,  H03L7/10 ,  G11C8/00 ,  G11C7/00

    CPC分类号： G11C7/222 ,  G11C7/22 ,  H03K5/131 ,  H03L7/0814 ,  H03L7/10

    摘要： An initial delay control data decision circuit detects to which portion of a variable delay circuit a pulse signal of an external clock signal of one cycle is propagated for a predetermined period of time, to determine an initial value for delay control data. Depending on the initial value for delay control data, a delay locked loop circuit configured of the variable delay circuit, a phase comparator circuit, a shift logic circuit, a delay control data holding circuit, a variable constant current circuit and a voltage generating circuit controls phasing of internal and external clock signals.

    摘要翻译： 初始延迟控制数据判定电路检测一个周期的外部时钟信号的脉冲信号在可变延迟电路的哪个部分传播预定的时间段，以确定延迟控制数据的初始值。 根据延迟控制数据的初始值，由可变延迟电路，相位比较器电路，移位逻辑电路，延迟控制数据保持电路，可变恒流电路和电压产生电路控制构成的延迟锁定环路电路 内部和外部时钟信号的定相。