公开(公告)号：US20200210080A1

公开(公告)日：2020-07-02

申请号：US16237134

申请日：2018-12-31

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer ,  Sean L. Manion ,  Jonathan Parry ,  Stephen Hanna ,  Qing Liang ,  Nadav Grosz ,  Christian M. Gyllenskog ,  Kulachet Tanpairoj

IPC: G06F3/06 ,  G06F12/02

Abstract: Apparatus and methods are disclosed, including using a memory controller to partition a memory array into a first portion and a second portion, the first portion and second portion having non-overlapping logical block addressing (LBA) ranges. The memory controller assigns a first granularity of a first logical-to-physical (L2P) mapping table entry for the first portion of the memory array designated for a first usage, and a second granularity of a second L2P mapping table entry for the second portion of the memory array designated for a second usage, where the second granularity is not equal to the first granularity. The memory controller stores the first granularity and the second granularity in the memory array, and stores at least a portion of the first L2P mapping table entry and the second L2P mapping table entry in an L2P cache of the memory controller.

公开(公告)号：US20200065186A1

公开(公告)日：2020-02-27

申请号：US16107187

申请日：2018-08-21

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer

IPC: G06F11/10 ,  G06F17/30

Abstract: Aspects of the present disclosure configure a memory sub-system to track error-correction parity calculations in the memory sub-system. For example, a memory sub-system controller of the memory sub-system can generate and use a first data structure to map one or more data chunks of an open data block to one or more buffers in a set of buffers for temporary storage of partial parity calculation results for the one or more data chunks, and generate and use a second data structure to map one or more data chunks of an open data block to one or more memory locations on non-volatile memory space (implemented by a set of memory components) for persistent storage of partial panty calculation results for the one or more data chunks.

公开(公告)号：US20200042452A1

公开(公告)日：2020-02-06

申请号：US16054096

申请日：2018-08-03

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer

IPC: G06F12/0866 ,  G06F12/0804 ,  G06F13/12 ,  G06F13/38 ,  G06F9/445 ,  G06F1/24

Abstract: Techniques are disclosed herein for providing accelerated recovery techniques of a memory device. Such techniques can allow for recovery of the memory device, such as, but not limited to, a flash memory device, following an unexpected reset event.

公开(公告)号：US12271310B2

公开(公告)日：2025-04-08

申请号：US17306419

申请日：2021-05-03

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer

IPC: G06F12/0804

Abstract: Devices and techniques for enhanced flush transfer efficiency in a storage device are described herein. A flush trigger for a user data write can be identified. Here, user data corresponds to the user data write and was stored in a buffer. The size of the user data stored in the buffer is smaller than a write width for a storage device subject to the write. The difference ins the user data size in the buffer and the write width is buffer free space. Additional data can be marshalled in response to the identification of the flush trigger. Here, the additional data size is less than or equal to the buffer free space. The user data and the additional data can then be written to the storage device.

公开(公告)号：US12204792B2

公开(公告)日：2025-01-21

申请号：US17396117

申请日：2021-08-06

Applicant: Micron Technology, Inc.

Inventor： Reshmi Basu ,  David Aaron Palmer ,  Jonathan S. Parry

IPC: G06F3/06 ,  G06F1/08

Abstract: Methods, systems, and devices for adaptive throughput monitoring are described. In some examples, a memory system may be associated with one or more clocks that are each associated with a respective subcomponent. When the memory system receives a plurality of commands, the memory system may determine a throughput of the commands. Based on the determined throughput, the memory system may adjust a rate of one or more of the clocks.

公开(公告)号：US12182027B2

公开(公告)日：2024-12-31

申请号：US18095782

申请日：2023-01-11

Applicant: Micron Technology, Inc.

Inventor： Deping He ,  David Aaron Palmer

IPC: G06F12/00 ,  G06F12/0893

Abstract: Methods, systems, and devices for cache block budgeting techniques are described. In some memory systems, a controller may configure a memory device with a cache. The cache may include a first subset of blocks configured to statically operate in a first mode and a second subset of blocks configured to dynamically switch between operating in the first mode and a second mode. A block operating in the second mode may be configured to store relatively more bits per memory cell than a block operating in the first mode. The controller may track and store, for each block of the second subset of blocks, a respective ratio of cycles performed in the first mode to cycles performed in the second mode. The controller may select a block from the second subset of blocks to switch between modes responsive to a trigger and based on the respective ratio for the block.

公开(公告)号：US12105959B2

公开(公告)日：2024-10-01

申请号：US17884429

申请日：2022-08-09

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer ,  Giuseppe Cariello ,  Fulvio Rori

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0629 ,  G06F3/0659 ,  G06F3/0679

Abstract: Methods, systems, and devices for suspending operations of a memory system are described. A memory system may be configured to perform a write operation to store data in a nonvolatile memory device, where the write operation includes storing information in one or more latches associated with the nonvolatile memory device; receive a suspend command to suspend performance of the write operation based on a request to perform a read operation associated with a higher-priority than the write operation; suspend the performance of the write operation based on receiving the suspend command; transmit the information stored in the one or more latches associated with the nonvolatile memory device to a host system based on suspending the performance of the write operation; and perform the read operation based at least in part on transmitting the information to the host system.

公开(公告)号：US11914897B2

公开(公告)日：2024-02-27

申请号：US17540546

申请日：2021-12-02

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0656 ,  G06F3/0679

Abstract: Devices and techniques for arbitrating operation of memory devices in a managed NAND memory system to conform the operation to a power budget. In an example, a method can include enabling a subset of memory die of a memory system having multiple memory die, starting an active timer for each active memory die, initializing execution of a buffered memory command at each active die based on a timestamp associated with the buffered memory command, and disabling a first memory die of the subset of memory die when the active timer for the first die expires to maintain compliance with a power budget of the memory system.

公开(公告)号：US20240061602A1

公开(公告)日：2024-02-22

申请号：US17892607

申请日：2022-08-22

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer

IPC: G06F3/06

CPC classification number: G06F3/0644 ,  G06F3/0659 ,  G06F3/0604 ,  G06F3/0679

Abstract: A system includes a memory device associated with a logical address space, and a processing device, operatively coupled to the memory device, to perform operations including providing, to a host system, power safety capability information for the logical address space, obtaining, from the host system, a power safety configuration for a partition of the logical address space, and providing, to the host system, an acknowledgement of receipt of the power safety configuration.

公开(公告)号：US11853602B2

公开(公告)日：2023-12-26

申请号：US17399771

申请日：2021-08-11

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679

Abstract: Methods, systems, and devices for adjusting a granularity associated with read disturb tracking are described. In some examples, a memory system may receive a set of read commands from a host system instructing the memory system to read data stored at a memory array. The memory system may track a quantity of executed read commands corresponding to a first portion of the memory array according to a first granularity and determine whether the quantity of read commands satisfies a threshold. If the quantity of read commands satisfies the threshold, the memory system may adjust the granularity for tracking executed read commands for the first portion from the first granularity to a second granularity. For example, the memory system may increase or decrease the granularity for tracking executed read commands for the first portion. The memory system may use the tracked quantities of executed read commands for read disturb remediation.