公开(公告)号：US11294585B2

公开(公告)日：2022-04-05

申请号：US17129087

申请日：2020-12-21

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer ,  Sean L. Manion ,  Jonathan Scott Parry ,  Stephen Hanna ,  Qing Liang ,  Nadav Grosz ,  Christian M. Gyllenskog ,  Kulachet Tanpairoj

IPC: G06F3/06 ,  G06F12/02

Abstract: Apparatus and methods are disclosed, including using a memory controller to partition a memory array into a first portion and a second portion, the first portion and second portion having non-overlapping logical block addressing (LBA) ranges. The memory controller assigns a first granularity of a first logical-to-physical (L2P) mapping table entry for the first portion of the memory array designated for a first usage, and a second granularity of a second L2P mapping table entry for the second portion of the memory array designated for a second usage, where the second granularity is not equal to the first granularity. The memory controller stores the first granularity and the second granularity in the memory array, and stores at least a portion of the first L2P mapping table entry and the second L2P mapping table entry in an L2P cache of the memory controller.

公开(公告)号：US20220214821A1

公开(公告)日：2022-07-07

申请号：US17702217

申请日：2022-03-23

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer ,  Sean L. Manion ,  Jonathan Scott Parry ,  Stephen Hanna ,  Qing Liang ,  Nadav Grosz ,  Chistian M. Gyllenskog ,  Kulachet Tanpairoj

IPC: G06F3/06 ,  G06F12/02

Abstract: Apparatus and methods are disclosed, including using a memory controller to partition a memory array into a first portion and a second portion, the first portion and second portion having non-overlapping logical block addressing (LBA) ranges. The memory controller assigns a first granularity of a first logical-to-physical (L2P) mapping table entry for the first portion of the memory array designated for a first usage, and a second granularity of a second L2P mapping table entry for the second portion of the memory array designated for a second usage, where the second granularity is not equal to the first granularity. The memory controller stores the first granularity and the second granularity in the memory array, and stores at least a portion of the first L2P mapping table entry and the second L2P mapping table entry in an L2P cache of the memory controller.

公开(公告)号：US20210109666A1

公开(公告)日：2021-04-15

申请号：US17129087

申请日：2020-12-21

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer ,  Sean L. Manion ,  Jonathan Scott Parry ,  Stephen Hanna ,  Qing Liang ,  Nadav Grosz ,  Christian M. Gyllenskog ,  Kulachet Tanpairoj

IPC: G06F3/06 ,  G06F12/02

Abstract: Apparatus and methods are disclosed, including using a memory controller to partition a memory array into a first portion and a second portion, the first portion and second portion having non-overlapping logical block addressing (LBA) ranges. The memory controller assigns a first granularity of a first logical-to-physical (L2P) mapping table entry for the first portion of the memory array designated for a first usage, and a second granularity of a second L2P mapping table entry for the second portion of the memory array designated for a second usage, where the second granularity is not equal to the first granularity. The memory controller stores the first granularity and the second granularity in the memory array, and stores at least a portion of the first L2P mapping table entry and the second L2P mapping table entry in an L2P cache of the memory controller.

公开(公告)号：US20200210080A1

公开(公告)日：2020-07-02

申请号：US16237134

申请日：2018-12-31

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer ,  Sean L. Manion ,  Jonathan Parry ,  Stephen Hanna ,  Qing Liang ,  Nadav Grosz ,  Christian M. Gyllenskog ,  Kulachet Tanpairoj

IPC: G06F3/06 ,  G06F12/02

Abstract: Apparatus and methods are disclosed, including using a memory controller to partition a memory array into a first portion and a second portion, the first portion and second portion having non-overlapping logical block addressing (LBA) ranges. The memory controller assigns a first granularity of a first logical-to-physical (L2P) mapping table entry for the first portion of the memory array designated for a first usage, and a second granularity of a second L2P mapping table entry for the second portion of the memory array designated for a second usage, where the second granularity is not equal to the first granularity. The memory controller stores the first granularity and the second granularity in the memory array, and stores at least a portion of the first L2P mapping table entry and the second L2P mapping table entry in an L2P cache of the memory controller.

公开(公告)号：US20240176549A1

公开(公告)日：2024-05-30

申请号：US18520387

申请日：2023-11-27

Applicant: Micron Technology, Inc.

Inventor： Roberto Izzi ,  Luca Porzio ,  Sean L. Manion ,  Massimo Zucchinali ,  Bryan D. Butler ,  Andrea Vigilante ,  Marco Onorato ,  Alfredo Palazzo

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0632 ,  G06F3/0674

Abstract: Methods, systems, and devices for latency reduction of boot procedures for memory systems are described. A memory system may receive a first command to perform a first reset of one or more components as part of a first phase of a boot procedure of a host system. The memory system may initiate an initialization process of a second phase of the boot procedure upon determining whether the value of a flag has been set from a first value to a second value. Upon completing the initialization process, the flag may be set to the first value. Parameters corresponding to the characteristics of the memory system may be communicated to the host system based on receiving a second command. The memory system may perform a configuration operation of a logical-to-physical mapping concurrently with communicating the parameters with the host system.

公开(公告)号：US11755214B2

公开(公告)日：2023-09-12

申请号：US17702217

申请日：2022-03-23

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer ,  Sean L. Manion ,  Jonathan Scott Parry ,  Stephen Hanna ,  Qing Liang ,  Nadav Grosz ,  Christian M. Gyllenskog ,  Kulachet Tanpairoj

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F3/0631 ,  G06F3/061 ,  G06F3/0679 ,  G06F12/0246 ,  G06F2212/7201 ,  G06F2212/7204

Abstract: Apparatus and methods are disclosed, including using a memory controller to partition a memory array into a first portion and a second portion, the first portion and second portion having non-overlapping logical block addressing (LBA) ranges. The memory controller assigns a first granularity of a first logical-to-physical (L2P) mapping table entry for the first portion of the memory array designated for a first usage, and a second granularity of a second L2P mapping table entry for the second portion of the memory array designated for a second usage, where the second granularity is not equal to the first granularity. The memory controller stores the first granularity and the second granularity in the memory array, and stores at least a portion of the first L2P mapping table entry and the second L2P mapping table entry in an L2P cache of the memory controller.