公开(公告)号：US12056518B2

公开(公告)日：2024-08-06

申请号：US17959724

申请日：2022-10-04

申请人： Micron Technology, Inc.

发明人： Qing Liang ,  Jonathan S. Parry ,  Kulachet Tanpairoj ,  Stephen Hanna

IPC分类号： G06F9/48 ,  G06F12/08 ,  G06F12/0875

CPC分类号： G06F9/485 ,  G06F12/0875 ,  G06F2212/1041

摘要： An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to receive a reset signal from a host computer system in communication with the memory system; identify, by decoding the reset signal, a host event specified by the reset signal; and process the identified host event.

公开(公告)号：US11755214B2

公开(公告)日：2023-09-12

申请号：US17702217

申请日：2022-03-23

申请人： Micron Technology, Inc.

发明人： David Aaron Palmer ,  Sean L. Manion ,  Jonathan Scott Parry ,  Stephen Hanna ,  Qing Liang ,  Nadav Grosz ,  Christian M. Gyllenskog ,  Kulachet Tanpairoj

IPC分类号： G06F3/06 ,  G06F12/02

CPC分类号： G06F3/0631 ,  G06F3/061 ,  G06F3/0679 ,  G06F12/0246 ,  G06F2212/7201 ,  G06F2212/7204

摘要： Apparatus and methods are disclosed, including using a memory controller to partition a memory array into a first portion and a second portion, the first portion and second portion having non-overlapping logical block addressing (LBA) ranges. The memory controller assigns a first granularity of a first logical-to-physical (L2P) mapping table entry for the first portion of the memory array designated for a first usage, and a second granularity of a second L2P mapping table entry for the second portion of the memory array designated for a second usage, where the second granularity is not equal to the first granularity. The memory controller stores the first granularity and the second granularity in the memory array, and stores at least a portion of the first L2P mapping table entry and the second L2P mapping table entry in an L2P cache of the memory controller.

公开(公告)号：US11675661B2

公开(公告)日：2023-06-13

申请号：US17882836

申请日：2022-08-08

申请人： Micron Technology, Inc.

发明人： Qing Liang

IPC分类号： G06F11/10 ,  G06F12/1009 ,  G06F3/06

CPC分类号： G06F11/1068 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/1009 ,  G06F2212/657

摘要： Disclosed in some examples are memory devices which increase a parallelism of host operations of a memory device. While a first block of data from a first stripe in a first memory die is being read, blocks of data belonging to a second stripe stored in memory dies other than the first memory die are concurrently read. This includes reading the parity value of the second stripe. The parity data, along with the blocks of data from the second stripe from dies other than the first die are then used to determine the block of data of the second stripe stored in the first memory die without actually reading the value from the block in the first memory die. This reconstruction may be done in parallel with additional read operations for other data performed on the first die.

公开(公告)号：US20230017388A1

公开(公告)日：2023-01-19

申请号：US17873850

申请日：2022-07-26

申请人： Micron Technology, Inc.

发明人： Qisong Lin ,  Shuai Xu ,  Jonathan S. Parry ,  Jeremy Binfet ,  Micheie Piccardi ,  Qing Liang

IPC分类号： G11C16/30 ,  G06F3/06 ,  G06F12/0875 ,  G11C16/10

摘要： Methods, systems, and devices for power architecture for non-volatile memory are described. A memory device may be configured to operate in a first mode and a second mode (e.g., a low power mode). When operating in the first mode, a voltage may be supplied from a power source (e.g., a power management integrated circuit) to a memory array and one or more associated components via a regulator. When the memory device transitions to operate in the second mode, some of the components supplied from the power source may be powered by a charge pump. Control information associated with the memory array may be stored to the one or more components (e.g., to a cache) that are powered by a charge pump.

公开(公告)号：US11550711B2

公开(公告)日：2023-01-10

申请号：US16565066

申请日：2019-09-09

申请人： Micron Technology, Inc.

发明人： Deping He ,  Nadav Grosz ,  Qing Liang ,  David Aaron Palmer

IPC分类号： G06F12/02

摘要： Devices and techniques for a dynamically adjusting a garbage collection workload are described herein. For example, memory device idle times can be recorded. From these recorded idle times, a metric can be derived. A current garbage collection workload can be divided into portions based on the metric. Then, a first portion of the divided garbage collection workload can be performed at a next idle time.

公开(公告)号：US20220179572A1

公开(公告)日：2022-06-09

申请号：US17682778

申请日：2022-02-28

申请人： Micron Technology, Inc.

发明人： Qing Liang ,  Deping He

IPC分类号： G06F3/06 ,  G06F9/4401 ,  G06F11/10 ,  G11C29/52

摘要： Several embodiments of memory devices and related methods for initializing such memory devices based on initialization information stored in NAND-based memory media. In one embodiment, a memory device can include a controller operably coupled to the memory media. The controller is configured to determine whether the initialization information stored at a region of the memory media is valid, initialize the memory device based at least in part on the initialization information when valid, and invalidate the initialization information stored at the region of the memory media by writing to the region of the memory media without first erasing the region of the memory media.

公开(公告)号：US20220113970A1

公开(公告)日：2022-04-14

申请号：US17558140

申请日：2021-12-21

申请人： Micron Technology, Inc.

发明人： Qing Liang ,  Nadav Grosz

IPC分类号： G06F9/30 ,  G06F3/06 ,  G06F9/48 ,  G06F12/1009

摘要： Devices and techniques are disclosed herein for more efficiently exchanging large amounts of data between a host and a storage system. In an example, a read command can optionally include a read-type indicator. The read-type indicator can allow for exchange of a large amount of data between the host and the storage system using a single read command.

公开(公告)号：US11216058B2

公开(公告)日：2022-01-04

申请号：US16511490

申请日：2019-07-15

申请人： Micron Technology, Inc.

发明人： Qing Liang ,  Jonathan Scott Parry

IPC分类号： G06F1/00 ,  G06F1/3287 ,  G06F1/28

摘要： Systems and methods are disclosed, including, after a first threshold time after entering an idle power mode of a storage system, without receiving a command from a host device over a communication interface, moving host data stored in volatile memory of the storage system to non-volatile memory of the storage system and transitioning a power mode of the storage system from an idle power mode to a deep idle power mode using control circuitry of the storage system, the deep idle power mode having a second power level lower than a first power level of the idle mode and a second exit latency higher than a first latency of the idle mode. The control circuitry can further determine that the storage system is ready to enter a power savings power mode and provide an indication of the determination using a unidirectional power state signal interface separate from the communication interface.

公开(公告)号：US20210373939A1

公开(公告)日：2021-12-02

申请号：US16889029

申请日：2020-06-01

申请人： Micron Technology, Inc.

发明人： Qing Liang ,  Jonathan S. Parry ,  Kulachet Tanpairoj ,  Stephen Hanna

IPC分类号： G06F9/48 ,  G06F12/0875

摘要： An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to receive a reset signal from a host computer system in communication with the memory system; identify, by decoding the reset signal, a host event specified by the reset signal; and process the identified host event.

公开(公告)号：US20210073121A1

公开(公告)日：2021-03-11

申请号：US16565066

申请日：2019-09-09

申请人： Micron Technology, Inc.

发明人： Deping He ,  Nadav Grosz ,  Qing Liang ,  David Aaron Palmer

IPC分类号： G06F12/02

摘要： Devices and techniques for a dynamically adjusting a garbage collection workload are described herein. For example, memory device idle times can be recorded. From these recorded idle times, a metric can be derived. A a current garbage collection workload can be divided into portions based on the metric. Then, a first portion of the divided garbage collection workload can be performed at a next idle time.