公开(公告)号：US20210358561A1

公开(公告)日：2021-11-18

申请号：US17443746

申请日：2021-07-27

Applicant: Micron Technology, Inc.

Inventor： Tingjun Xie ,  Zhengang Chen

IPC: G11C29/50 ,  G06F11/07

Abstract: A processing device in a memory system determines a first error rate corresponding to a first set of write-to-read delay times at a first end of a range of write-to-read delay times for a memory device and a second error rate corresponding to a second set of write-to-read delay times at a second end of the range of write-to-read delay times, and determines whether a ratio of the first error rate to the second error rate satisfies a threshold criterion. Responsive to the ratio of the first error rate to the second error rate not satisfying the threshold criterion, the processing device adjusts a read voltage level associated with the range of write-to-read delay times

公开(公告)号：US20210286559A1

公开(公告)日：2021-09-16

申请号：US17332605

申请日：2021-05-27

Applicant: Micron Technology, Inc.

Inventor： Tingjun Xie ,  Zhengang Chen

IPC: G06F3/06 ,  G11C7/10 ,  G11C7/22

Abstract: A method described herein involves identifying a first time associated with a read operation that retrieves data of a write unit at a memory sub-system, identifying a second time associated with a write operation that stored the data of the write unit at the memory sub-system, and performing a refresh operation for the data of the write unit at the memory sub-system based on a difference between the first time associated with the read operation and the second time associated with the write operation.

公开(公告)号：US20210286558A1

公开(公告)日：2021-09-16

申请号：US17332187

申请日：2021-05-27

Applicant: Micron Technology, Inc.

Inventor： Zhengang Chen ,  Tingjun Xie

IPC: G06F3/06 ,  G11C16/10 ,  G06F16/245 ,  G11C16/26

Abstract: A system includes a memory component; and a processing device, operatively coupled with the memory component. The processing device is to perform operations including receiving a read request with respect to data stored at a physical address of the memory component; determining whether an indicator of the physical address is stored in a write transaction catalog; in response to determining that the physical address is stored in the write transaction catalog, determining a time difference between when the read request was received and when the data was written; reading the data stored at the physical address using a first read voltage level in response to determining that the time difference is less than a threshold criterion; and reading the data stored at the physical address using a second read voltage level in response to determining that the time difference is equal to or greater than the threshold criterion.

公开(公告)号：US11107550B2

公开(公告)日：2021-08-31

申请号：US16510483

申请日：2019-07-12

Applicant: Micron Technology, Inc.

Inventor： Tingjun Xie ,  Zhengang Chen

IPC: G11C29/50 ,  G06F11/07

Abstract: A processing device in a memory system identifies a first range of a plurality of write-to-read delay ranges for the memory component, wherein the first range represents a plurality of write-to-read delay times and has an associated read voltage level used to perform a read operation on a segment of the memory component having a write-to-read delay time that falls within the first range. The processing device further identifies a first set of the plurality of write-to-read delay times at a first end of the first range and a second set of the plurality of write-to-read delay times at a second end of the first range, and determines a first error rate for the memory component corresponding to the first set of the plurality of write-to-read delay times and a second error rate for the memory component corresponding to the second set of the plurality of write-to-read delay times. The processing device determines whether a correspondence between the first error rate and the second error rate satisfies a first threshold criterion, and, responsive to the correspondence between the first error rate and the second error rate not satisfying the first threshold criterion, modifies the read voltage level associated with the first range.

公开(公告)号：US20210233603A1

公开(公告)日：2021-07-29

申请号：US17301747

申请日：2021-04-13

Applicant: Micron Technology, Inc.

Inventor： Tingjun Xie ,  Zhengang Chen

IPC: G11C29/50 ,  G06F3/06

Abstract: A processing device in a memory sub-system determines a write-to-read delay time for a segment of a memory device read during a first read operation using a first read voltage level. The processing device further determines that the write-to-read delay time is associated with a second read voltage level and performs a read refresh operation on at least a portion of the segment of the memory device using the second read voltage level.

公开(公告)号：US20210019084A1

公开(公告)日：2021-01-21

申请号：US16514820

申请日：2019-07-17

Applicant: Micron Technology, Inc.

Inventor： Tingjun Xie ,  Zhengang Chen

IPC: G06F3/06 ,  G11C7/10 ,  G11C7/22

Abstract: A read operation can be performed to retrieve data of a write unit at a memory sub-system. An indication of a time of the performance of the read operation can be received. Another indication of another time of a performance of a write operation to store the data of the write unit at the memory sub-system can be received. A difference between the time of the performance of the read operation and the another time of the performance of the write operation can be determined. A refresh operation can be performed for the data of the write unit at the memory sub-system based on the difference between the time of the performance of the read operation and the another time of the performance of the write operation

公开(公告)号：US20200183783A1

公开(公告)日：2020-06-11

申请号：US16215248

申请日：2018-12-10

Applicant: Micron Technology, Inc.

Inventor： Tingjun Xie ,  Zhengang Chen

IPC: G06F11/10 ,  G11C16/26 ,  G11C16/10 ,  G11C29/52 ,  G06F3/06

Abstract: Described herein are embodiments related to one-direction error recovery flow (ERF) operations on memory components of memory systems. A processing device determines that data from a read operation is not successfully decoded because of a partial write of the data. The partial write results from a number of memory cells written as a first state and read as a second state. The processing device performs a one-direction ERF on the memory cells by monotonically adjusting a read voltage level for one or more re-read operations from a first discrete read voltage level towards a second read voltage level in a first direction until the data from the one or more re-read operations is successfully decoded. The first direction corresponds to an opposite direction of a state shift of the partial write. The processing device can also can determine a directional EBC and perform a refresh write if necessary.

公开(公告)号：US20200026595A1

公开(公告)日：2020-01-23

申请号：US16039683

申请日：2018-07-19

Applicant: Micron Technology, Inc.

Inventor： Wei Wang ,  Jiangli Zhu ,  Ying Yu Tai ,  Ning Chen ,  Zhengang Chen ,  Cheng Yuan Wu

IPC: G06F11/07 ,  G06F11/10 ,  G11C29/52

Abstract: A read operation to retrieve data from memory component and that bypasses a prior search for the data at a buffer in a read data path associated with the read operation can be performed. Responsive to performing the read operation that bypasses the prior search for the data at the buffer, the data is returned to a host system.