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1.发明公开公开(公告)号：US20240347116A1
公开(公告)日：2024-10-17
申请号：US18755046
申请日：2024-06-26
Applicant: Micron Technology, Inc.
Inventor： Wei Wang , Seungjune Jeon , Yang Liu , Charles See Yeung Kwong
CPC classification number: G11C16/3431 , G11C16/0483
Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising identifying one or more valid pages of a first block, the first block being associated with a first management unit of the memory device; responsive to determining that a data integrity metric value associated with the first block satisfies a threshold criterion, causing the memory device to copy data from the one or more valid pages to a destination set of pages associated with a second block of a second management unit; marking each page of the one or more valid pages as invalid; and performing an error correcting operation, using one or more invalid pages of the first block, on a third block of the first management unit.
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公开(公告)号：US11726815B2
公开(公告)日：2023-08-15
申请号：US16913751
申请日：2020-06-26
Applicant: Micron Technology, Inc.
Inventor： Jason Duong , Chih-Kuo Kao , Jiangli Zhu , Ying Yu Tai , Wei Wang
CPC classification number: G06F9/4881 , G06F3/0611 , G06F3/0644 , G06F3/0659 , G06F3/0683 , G06F9/3855
Abstract: Methods, systems, and devices for scheduling command execution are described. A memory sub-system can schedule command execution according to a type of command received. For a read operation, a memory sub-system can receive read commands for multiple memory dice. The memory sub-system can select a first memory die and execute a first set of read commands associated with the first memory die. The memory sub-system can then select a second memory die and execute a second set of read commands associated with the second memory die.
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公开(公告)号：US20230062949A1
公开(公告)日：2023-03-02
申请号：US17462289
申请日：2021-08-31
Applicant: Micron Technology, Inc.
Inventor： Huapeng G. Guan , Ximin Shan , Yipei Yu , Wei Wang
Abstract: A system for file system data access can include memory devices including a non-volatile memory device, as well as a processing device, operatively coupled with the memory devices to perform operations including receiving a file system (FS) write command and determining whether a write count of a physical super management unit (PSMU) of the non-volatile memory device satisfies a threshold criterion. The operations can include, recording a change of a super management unit (SMU) mapping for FS data of an FS mapping table, where the FS mapping table is a portion of a logical-to-physical (L2P) mapping table and performing a move of SMU data corresponding to the change of the SMU mapping. They can also include creating a backup copy of the FS mapping table on the non-volatile memory device, and restoring the FS mapping table from the backup copy of the FS mapping table.
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公开(公告)号：US11526395B2
公开(公告)日：2022-12-13
申请号：US17100571
申请日：2020-11-20
Applicant: Micron Technology, Inc.
Inventor： Wei Wang , Jiangli Zhu , Ying Yu Tai , Ning Chen , Zhengang Chen , Cheng Yuan Wu
Abstract: A read operation to retrieve data stored at a memory device is performed. Whether the data retrieved from the memory device includes an error that is not correctable is determined. Responsive to determining that the data retrieved from the memory device comprises the error that is not correctable, a buffer in a data path along which a write operation was performed to write the data at the memory device is searched for the data.
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公开(公告)号：US11526295B2
公开(公告)日：2022-12-13
申请号：US16934406
申请日：2020-07-21
Applicant: Micron Technology, Inc.
Inventor： Murong Lang , Tingjun Xie , Wei Wang , Frederick Adi , Zhenming Zhou , Jiangli Zhu
IPC: G06F3/06
Abstract: A first operating characteristic and a second operating characteristic of a memory sub-system are determined. A write-to-read delay time is set in view of the first operating characteristic and the second operating characteristic. A read operation associated with a memory unit is executed following a period of at least the write-to-read delay time from a time of an execution of a write operation associated with the memory unit.
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Patent Agency Ranking
公开(公告)号：US20220326856A1
公开(公告)日：2022-10-13
申请号：US17730958
申请日：2022-04-27
Applicant: Micron Technology, Inc.
Inventor： Fangfang Zhu , Wei Wang , Jiangli Zhu , Ying Yu Tai
IPC: G06F3/06
Abstract: Methods, systems, and devices for memory can include techniques for identifying first quantities of write counts for a first plurality of super management units (SMUs) in a mapped region of a memory sub-system, identifying, by a hardware component of the memory sub-system, a first SMU of the first plurality that includes a fewest quantity of write counts of the first quantity of write counts, and performing a wear-leveling operation based at least in part on a first quantity of write counts of the first SMU of the first plurality in the mapped region being less than a second quantity of writes counts of a second SMU of a second plurality of SMUs in an unmapped region of the memory sub-system.
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公开(公告)号：US11320987B2
公开(公告)日：2022-05-03
申请号：US16555997
申请日：2019-08-29
Applicant: Micron Technology, Inc.
Inventor： Fangfang Zhu , Wei Wang , Jiangli Zhu , Ying Yu Tai
IPC: G06F3/06
Abstract: Methods, systems, and devices for memory can include techniques for identifying first quantities of write counts for a first plurality of super management units (SMUs) in a mapped region of a memory sub-system, identifying, by a hardware component of the memory sub-system, a first SMU of the first plurality that includes a fewest quantity of write counts of the first quantity of write counts, and performing a wear-leveling operation based at least in part on a first quantity of write counts of the first SMU of the first plurality in the mapped region being less than a second quantity of writes counts of a second SMU of a second plurality of SMUs in an unmapped region of the memory sub-system.
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公开(公告)号：US11294750B2
公开(公告)日：2022-04-05
申请号：US16784926
申请日：2020-02-07
Applicant: Micron Technology, Inc.
Inventor： Fangfang Zhu , Ying Yu Tai , Jiangli Zhu , Wei Wang
IPC: G06F11/07
Abstract: In an embodiment, a system includes a plurality of memory components and a processing device. The processing device includes a command-lifecycle logger component that is configured to perform command-lifecycle-logging operations, which include detecting a triggering event for logging command-lifecycle debugging data, and responsively logging command-lifecycle debugging data. Logging command-lifecycle debugging data includes generating the command-lifecycle debugging data and storing the generated command-lifecycle debugging data in data storage.
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公开(公告)号：US20220100605A1
公开(公告)日：2022-03-31
申请号：US17445345
申请日：2021-08-18
Applicant: Micron Technology, Inc.
Inventor： Frederick Adi , Zhenlei Shen , Wei Wang
Abstract: A processing device in a memory sub-system receives an indication that a write back operation was performed for a management unit in a memory device. Responsive to receiving the indication that the write back operation was performed, the processing device initiates a read verify operation for the management unit and receives an indication of a number of write back errors associated with the management unit during the read verify operation. The processing device further determines whether the number of write back errors satisfies a read verify threshold criterion, and responsive to the number of write back errors satisfying the read verify threshold criterion, remaps the management unit to a different location on the memory device.
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公开(公告)号：US20220075682A1
公开(公告)日：2022-03-10
申请号：US17531091
申请日：2021-11-19
Applicant: Micron Technology, Inc.
Inventor： Jiangli Zhu , Ying Yu Tai , Fangfang Zhu , Wei Wang
Abstract: In an embodiment, a system includes a plurality of memory components and a processing device that is operatively coupled with the plurality of memory components. The processing device includes a host interface, an access management component, a media management component (MMC), and an MMC-restart manager that is configured to perform operations including detecting a triggering event for restarting the MMC, and responsively performing MMC-restart operations that include suspending operation of the access management component; determining whether the MMC is operating, and if so then suspending operation of the MMC; resetting the MMC; resuming operation of the MMC; and resuming operation of the access management component.
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