Programmable extended compression mask for dynamic trace
    91.
    发明授权
    Programmable extended compression mask for dynamic trace 有权
    可编程扩展压缩掩模,用于动态跟踪

    公开(公告)号:US07162552B2

    公开(公告)日:2007-01-09

    申请号:US10302189

    申请日:2002-11-22

    CPC分类号: G06F11/3636 G06F11/3476

    摘要: This invention provides trace address compression by comparing respective bytes of a current trace address with a stored comparison address. Only the least significant bytes of the current trace address that do not match the comparison address or are less significant than any section of the current trace address that does not match the comparison address are transmitted. This sometimes reduces the amount of data that needs to be transmitted. The comparison address is specified by a central processing unit via a memory mapped register write operation.

    摘要翻译: 本发明通过将当前跟踪地址的各个字节与存储的比较地址进行比较来提供跟踪地址压缩。 只有当前跟踪地址中与比较地址不匹配或者比当前跟踪地址与比较地址不匹配的任何部分不太重要的最低有效字节被传送。 这有时会减少需要传输的数据量。 比较地址由中央处理单元通过存储器映射寄存器写入操作指定。

    Multi-Port Trace Data Handling
    92.
    发明申请
    Multi-Port Trace Data Handling 有权
    多端口跟踪数据处理

    公开(公告)号:US20060288254A1

    公开(公告)日:2006-12-21

    申请号:US11467735

    申请日:2006-08-28

    IPC分类号: G06F11/00

    CPC分类号: G06F11/3636 G06F11/3656

    摘要: A method of trace data compression receives trace data on a first port and a second port stores a prior data value. If trace data is received on only one port, then that trace data is transmitted as an indication of matching and non-matching sections between the current trace data and the stored data value and the non-matching sections of the current trace data on the one port. If trace data is received on both ports, then the first port trace data is transmitted relative to the prior stored value and the second port trace data is transmitted relative to the first port trace data. The stored prior data is reset to zero upon each initiation or termination of trace data on either port. The stored prior value is set to the second port value or the first port value if no second port value is received.

    摘要翻译: 跟踪数据压缩的方法在第一端口上接收跟踪数据,而第二端口存储先前的数据值。 如果仅在一个端口上接收到跟踪数据,则该跟踪数据作为当前跟踪数据与存储的数据值之间的匹配和非匹配部分的指示以及当前跟踪数据的不匹配部分在一个端口上发送 港口。 如果在两个端口上都接收到跟踪数据,则相对于先前存储的值传输第一个端口跟踪数据,并且相对于第一个端口跟踪数据传输第二个端口跟踪数据。 在任一端口上的跟踪数据的每次启动或终止时,存储的先前数据被重置为零。 如果没有接收到第二个端口值,则将存储的先前值设置为第二个端口值或第一个端口值。

    Behavior of Trace in Non-Emulatable Code
    93.
    发明申请
    Behavior of Trace in Non-Emulatable Code 有权
    痕迹行为在不可代码的代码

    公开(公告)号:US20060255980A1

    公开(公告)日:2006-11-16

    申请号:US11383543

    申请日:2006-05-16

    IPC分类号: H03M7/34

    CPC分类号: G06F21/52

    摘要: Code will switch to secure code via an exception only. All PC and data trace will be turned off during secure code. This will occur regardless of trace being in standard trace mode or event profiling mode. Timing, if on, will switch to standby mode. On return from the secure code, the switches that were already on will switch back and turn on. The address reported in the end sync point will be the address 0x01. Since this is an illegal address, this information is sufficient to indicate an end sync point was caused in secure code.

    摘要翻译: 代码将仅通过异常切换到安全代码。 所有PC和数据跟踪将在安全代码期间关闭。 无论跟踪在标准跟踪模式还是事件分析模式下,都会发生这种情况。 如果开启,则会切换到待机模式。 从安全代码返回时,已经开启的开关将切换回并打开。 报告在最后同步点的地址将是地址0x01。 由于这是一个非法的地址,所以这个信息足以表明在安全代码中造成结束同步点。

    Enabling Trace and Event Selection Procedures Independent of the Processor and Memory Variations
    94.
    发明申请
    Enabling Trace and Event Selection Procedures Independent of the Processor and Memory Variations 审中-公开
    启用与处理器和内存变化无关的跟踪和事件选择过程

    公开(公告)号:US20060255978A1

    公开(公告)日:2006-11-16

    申请号:US11383539

    申请日:2006-05-16

    申请人: Manisha Agarwala

    发明人: Manisha Agarwala

    IPC分类号: H03M7/00

    CPC分类号: G06F11/3636

    摘要: The event selection process has a variable set of signals going to a group of multiplexers (referred to as AEG). The output of the AEG is sent to trace, to be encoded and sent out in the trace stream. In order to make the AEG generic, a small logic block at the AEG inputs converts the inputs to a standard format required by the AEG. The entire system after the AEG remains generic and useable with various CPU and memory architectures.

    摘要翻译: 事件选择过程具有到一组多路复用器(称为AEG)的可变信号组。 AEG的输出被发送到跟踪,被编码并在跟踪流中发送出去。 为了使AEG通用,AEG输入端的一个小逻辑块将输入转换为AEG所需的标准格式。 AEG之后的整个系统仍然是通用的,可用于各种CPU和内存架构。

    Multi-port trace data handling
    95.
    发明授权
    Multi-port trace data handling 有权
    多端口跟踪数据处理

    公开(公告)号:US07127387B2

    公开(公告)日:2006-10-24

    申请号:US10302193

    申请日:2002-11-22

    IPC分类号: G06F9/455 G06F17/50

    CPC分类号: G06F11/3636 G06F11/3656

    摘要: A method of trace data compression receives trace data on a first port and a second port stores a prior data value. If trace data is received on only one port, then that trace data is transmitted as an indication of matching and non-matching sections between the current trace data and the stored data value and the non-matching sections of the current trace data on the one port. If trace data is received on both ports, then the first port trace data is transmitted relative to the prior stored value and the second port trace data is transmitted relative to the first port trace data. The stored prior data is reset to zero upon each initiation or termination of trace data on either port. The stored prior value is set to the second port value or the first port value if no second port value is received.

    摘要翻译: 跟踪数据压缩的方法在第一端口上接收跟踪数据,而第二端口存储先前的数据值。 如果仅在一个端口上接收到跟踪数据,则该跟踪数据作为当前跟踪数据与存储的数据值之间的匹配和非匹配部分的指示以及当前跟踪数据的不匹配部分在一个端口上发送 港口。 如果在两个端口上都接收到跟踪数据,则相对于先前存储的值传输第一个端口跟踪数据,并且相对于第一个端口跟踪数据传输第二个端口跟踪数据。 在任一端口上的跟踪数据的每次启动或终止时,存储的先前数据被重置为零。 如果没有接收到第二个端口值,则将存储的先前值设置为第二个端口值或第一个端口值。

    Reporting a Saturated Counter Value
    96.
    发明申请
    Reporting a Saturated Counter Value 有权
    报告饱和计数器值

    公开(公告)号:US20060200805A1

    公开(公告)日:2006-09-07

    申请号:US11383335

    申请日:2006-05-15

    IPC分类号: G06F9/44

    CPC分类号: G06F11/261

    摘要: A saturating count counts received event signals up to a first predetermined number. An overflow counter counts overflows up to a second predetermined number. The counter indicates overflow when the overflow count is non-zero and saturates and stops counting at a maximum count when the overflow count reaches the second predetermined number. The counter can be read via a register read operation. The sum of the sum of the first predetermined number of bits and the second predetermined number of bits being an integral multiple of 8 bits.

    摘要翻译: 饱和计数将接收的事件信号计数到第一预定数量。 溢出计数器计数溢出到第二预定数量。 当溢出计数达到第二个预定数量时,计数器指示溢出计数不为零并饱和,并以最大计数停止计数。 可以通过寄存器读取操作读取计数器。 第一预定位数和第二预定位数之和为8位的整数倍的总和。

    Adder-based base cell for field programmable gate arrays
    97.
    发明授权
    Adder-based base cell for field programmable gate arrays 失效
    用于现场可编程门阵列的基于加法器的基电池

    公开(公告)号:US5488315A

    公开(公告)日:1996-01-30

    申请号:US369060

    申请日:1995-01-05

    摘要: An adder-based base cell (10) is provided for field programmable gate arrays. The base cell (10) includes a first inverter (13) operable to receive a first input signal (A). A first NAND gate (12) is coupled to the first inverter (13) and is operable to receive a second input signal (B). A first 2:1 multiplexer (14) is coupled to the first NAND gate (12) and is operable to receive a third input signal (C). The output of the first 2:1 multiplexer (14) represents a first function (F1). A second inverter (17) is operable to receive a fourth input signal (D). A second NAND gate (16) is coupled to the second inverter (17) and is operable to receive a fifth input signal (E). An XOR gate (18) is coupled to the second NAND gate (16), is operable to receive a sixth input signal (F), and is coupled to the first 2:1 multiplexer (14). The output of the XOR gate represents a partial sum function (PS.sub.-- 1). A second 2:1 multiplexer (19) is operable to receive a seventh input signal (G), is operable to receive an eighth input signal (H) and is coupled to the XOR gate (18). The output of the second 2:1 multiplexer (19) represents a second function (F2).

    摘要翻译: 为现场可编程门阵列提供基于加法器的基电池(10)。 基站(10)包括可操作以接收第一输入信号(A)的第一反相器(13)。 第一NAND门(12)耦合到第一反相器(13)并且可操作以接收第二输入信号(B)。 第一2:1多路复用器(14)耦合到第一与非门(12)并且可操作以接收第三输入信号(C)。 第一2:1多路复用器(14)的输出表示第一功能(F1)。 第二逆变器(17)可操作以接收第四输入信号(D)。 第二NAND门(16)耦合到第二反相器(17)并且可操作以接收第五输入信号(E)。 XOR门(18)耦合到第二与非门(16),可操作以接收第六输入信号(F),并耦合到第一2:1复用器(14)。 XOR门的输出表示部分和函数(PS-1)。 第二2:1复用器(19)可操作以接收第七输入信号(G),可操作以接收第八输入信号(H)并耦合到异或门(18)。 第二2:1复用器(19)的输出表示第二功能(F2)。