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公开(公告)号：US07590974B2
公开(公告)日：2009-09-15
申请号：US11456990
申请日：2006-07-12
IPC分类号： G06F9/44
CPC分类号： G06F11/3636 , G06F11/3652
摘要： A method of tracing data processor activity with recover from detection of trace stream corruption. If the first trace data following detection of corruption is not a program counter sync point, then the trace transmits an indication of the current program counter address in an offset format from the program counter address of a last transmitted program counter sync point and then transmits trace data in event offset format. If the first trace data following detection of corruption is a program counter sync point, then the trace transmits trace data in event offset format.
摘要翻译： 追踪数据处理器活动的方法，从检测到跟踪流损坏中恢复。 如果检测到损坏后的第一个跟踪数据不是程序计数器同步点，则跟踪以最后发送的程序计数器同步点的程序计数器地址的偏移格式发送当前程序计数器地址的指示，然后发送跟踪 事件偏移格式的数据。 如果检测到损坏后的第一个跟踪数据是程序计数器同步点，则跟踪将以事件偏移格式发送跟踪数据。
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2.发明授权公开(公告)号：US07133821B2
公开(公告)日：2006-11-07
申请号：US10302191
申请日：2002-11-22
申请人： Manisha Agarwala , Maria B. H. Gill
发明人： Manisha Agarwala , Maria B. H. Gill
CPC分类号： G06F11/3636 , G06F11/3656
摘要： A method of scheduling trace packets in an integrated circuit generating trace packets of plural types stores trace data in respective first-in-first-out buffers. If a timing trace data first-in-first-out buffer is empty, timing trace data packet is transmitted. If a program counter overall data first-in-first-out buffer is not empty and the processor is at a data interruptible boundary, a program counter data packet is transmitted. If data first-in-first-out buffer is not empty, a data packet is transmitted. The program counter data packets include program counter sync data, program counter exception data, program counter relative branch data and program counter absolute branch data.
摘要翻译： 一种在产生多种类型的跟踪分组的集成电路中调度跟踪分组的方法将跟踪数据存储在相应的先进先出缓冲器中。 如果定时跟踪数据先进先出缓冲器为空，则发送定时跟踪数据包。 如果程序计数器的总体数据先进先出缓冲器不为空并且处理器处于数据可中断边界，则发送程序计数器数据分组。 如果数据先进先出缓冲器不为空，则传输数据包。 程序计数器数据包包括程序计数器同步数据，程序计数器异常数据，程序计数器相对分支数据和程序计数器绝对分支数据。
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公开(公告)号：US06230278B1
公开(公告)日：2001-05-08
申请号：US08850872
申请日：1997-05-02
申请人： Stephen (Hsiao Yi) Li , Jonathan Rowlands , Fuk Ho Pius Ng , Maria B. H. Gill , Frank L. Laczko, Sr. , Dong-Seok Youm , David (Shiu) W. Kam
发明人： Stephen (Hsiao Yi) Li , Jonathan Rowlands , Fuk Ho Pius Ng , Maria B. H. Gill , Frank L. Laczko, Sr. , Dong-Seok Youm , David (Shiu) W. Kam
IPC分类号： G06F128
CPC分类号： G06F9/3879 , G06F1/3203 , G06F1/3287 , G06F9/30018 , G06F9/30145 , G06F9/30167 , G06F9/355 , G06F9/3877 , Y02D10/171
摘要： A data processing device is provided which has multiprocessors that can be configured on a cycle by cycle basis as loosely coupled or tightly coupled. Bit-stream Processing Unit (BPU) 110 executes instructions from ROM 112 and accesses data from RAM 111. Similarly, Arithmetic Unit (AU) 120 executes instructions from ROM 122 and accesses data from RAM 121. Both processor operate in parallel and exchange data by accessing RAM 121. AU 120 can receive an instruction directive from BPU 110 directing it to perform a selected sequence of instructions in a loosely coupled manner. AU 120 can also receive an instruction directive from BPU 110 directing that a portion of AU 120 operationally replace a portion of BPU 110 for the duration of one instruction which allows data to be passed directly between the processors in a tightly coupled manner.
摘要翻译： 提供了一种数据处理装置，其具有可以以逐周期为基础配置为松散耦合或紧密耦合的多处理器。 位流处理单元（BPU）110执行来自ROM 112的指令并从RAM 111访问数据。类似地，算术单元（AU）120执行来自ROM 122的指令并从RAM 121访问数据。两个处理器并行操作并且通过 访问RAM 121.AU 120可以从BPU 110接收指令，指示它以松散耦合的方式执行选定的指令序列。 AU 120还可以接收来自BPU 110的指令，指示AU 120的一部分在一个指令的持续时间内可操作地替换BPU 110的一部分，这允许以紧密耦合的方式直接在处理器之间传递数据。
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公开(公告)号：US07127387B2
公开(公告)日：2006-10-24
申请号：US10302193
申请日：2002-11-22
CPC分类号： G06F11/3636 , G06F11/3656
摘要： A method of trace data compression receives trace data on a first port and a second port stores a prior data value. If trace data is received on only one port, then that trace data is transmitted as an indication of matching and non-matching sections between the current trace data and the stored data value and the non-matching sections of the current trace data on the one port. If trace data is received on both ports, then the first port trace data is transmitted relative to the prior stored value and the second port trace data is transmitted relative to the first port trace data. The stored prior data is reset to zero upon each initiation or termination of trace data on either port. The stored prior value is set to the second port value or the first port value if no second port value is received.
摘要翻译： 跟踪数据压缩的方法在第一端口上接收跟踪数据，而第二端口存储先前的数据值。 如果仅在一个端口上接收到跟踪数据，则该跟踪数据作为当前跟踪数据与存储的数据值之间的匹配和非匹配部分的指示以及当前跟踪数据的不匹配部分在一个端口上发送 港口。 如果在两个端口上都接收到跟踪数据，则相对于先前存储的值传输第一个端口跟踪数据，并且相对于第一个端口跟踪数据传输第二个端口跟踪数据。 在任一端口上的跟踪数据的每次启动或终止时，存储的先前数据被重置为零。 如果没有接收到第二个端口值，则将存储的先前值设置为第二个端口值或第一个端口值。
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公开(公告)号：US06985783B2
公开(公告)日：2006-01-10
申请号：US09827644
申请日：2001-04-06
CPC分类号： G06F9/355 , G06F9/3004 , G06F9/30061 , G06F9/30167 , G06F9/322 , G06F9/325 , G06F9/345 , G06F9/35 , G06F9/383
摘要： A data processing device is provided with an indexed-immediate addressing mode for processing streams of data. An instruction register 900 receives an instruction for execution. Decoding circuitry 913 selects a register specified by a field in an instruction to provide an index value. An immediate field from the instruction is combined with the index value by multiplexor 910 to form an address which can be used to access a data value or to form a target address for a branch instruction. Mux control 915 parses the immediate value to determine how to combine the immediate value and the index value.
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公开(公告)号：US08832318B2
公开(公告)日：2014-09-09
申请号：US11563821
申请日：2006-11-28
CPC分类号： G06F11/3636 , G06F11/3656
摘要： Data streams are generated for tracing target processor activity. When multiple streams are on, they are written at different times into their individual FIFO. It is possible that for a specific stream, the length and fields of the data that should be exported vary. This invention is a scheme to send out only the relevant fields.
摘要翻译： 生成跟踪目标处理器活动的数据流。 当多个流打开时，它们会在不同的时间被写入其各自的FIFO。 对于特定的流，可能导出的数据的长度和字段可能不同。 本发明是仅发出相关领域的方案。
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公开(公告)号：US07716034B2
公开(公告)日：2010-05-11
申请号：US11467735
申请日：2006-08-28
CPC分类号： G06F11/3636 , G06F11/3656
摘要： A method of trace data compression receives trace data on a first port and a second port stores a prior data value. If trace data is received on only one port, then that trace data is transmitted as an indication of matching and non-matching sections between the current trace data and the stored data value and the non-matching sections of the current trace data on the one port. If trace data is received on both ports, then the first port trace data is transmitted relative to the prior stored value and the second port trace data is transmitted relative to the first port trace data. The stored prior data is reset to zero upon each initiation or termination of trace data on either port. The stored prior value is set to the second port value or the first port value if no second port value is received.
摘要翻译： 跟踪数据压缩的方法在第一端口上接收跟踪数据，而第二端口存储先前的数据值。 如果仅在一个端口上接收到跟踪数据，则该跟踪数据作为当前跟踪数据与存储的数据值之间的匹配和非匹配部分的指示以及当前跟踪数据的不匹配部分在一个端口上发送 港口。 如果在两个端口上都接收到跟踪数据，则相对于先前存储的值传输第一个端口跟踪数据，并且相对于第一个端口跟踪数据传输第二个端口跟踪数据。 在任一端口上的跟踪数据的每次启动或终止时，存储的先前数据被重置为零。 如果没有接收到第二个端口值，则将存储的先前值设置为第二个端口值或第一个端口值。
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8.发明授权Tracing program counter addresses using native program counter format and instruction count format 有权使用本地程序计数器格式和指令计数格式跟踪程序计数器地址公开(公告)号：US07318176B2
公开(公告)日：2008-01-08
申请号：US11383337
申请日：2006-05-15
申请人： Manisha Agarwala , Bryan Thome , John M. Johnsen , Gary L. Swoboda , Lewis Nardini , Maria B. H. Gill
发明人： Manisha Agarwala , Bryan Thome , John M. Johnsen , Gary L. Swoboda , Lewis Nardini , Maria B. H. Gill
IPC分类号： G06F11/00
CPC分类号： G06F11/3636 , G06F11/3656
摘要： A method of tracing program counter activity in a data processor periodically transmits a program counter sync point including the current program counter address. Between sync points the program counter address is indicated by a program counter offset relative to the last program counter sync point. The program counter offset is sent as integral number of sections of a predetermined number of bits. Program counter sync points are transmitted often enough so that the program counter offset requires at most one less section than the program counter address.
摘要翻译： 在数据处理器中跟踪程序计数器活动的方法周期性地发送包括当前程序计数器地址的程序计数器同步点。 在同步点之间，程序计数器地址由相对于最后一个程序计数器同步点的程序计数器偏移指示。 程序计数器偏移作为整数个预定位数的部分发送。 程序计数器的同步点经常被传送到足够多的程序计数器偏移量至少比程序计数器地址少一个部分。
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公开(公告)号：US07162411B2
公开(公告)日：2007-01-09
申请号：US10302026
申请日：2002-11-22
CPC分类号： G06F11/3636 , G06F11/3656
摘要： Data streams are generated for tracing target processor activity. When multiple streams are on, they are written at different times into their individual FIFO. It is possible that for a specific stream, the length and fields of the data that should be exported vary. This invention is a scheme to send out only the relevant fields.
摘要翻译： 生成跟踪目标处理器活动的数据流。 当多个流打开时，它们会在不同的时间被写入其各自的FIFO。 对于特定的流，可能导出的数据的长度和字段可能不同。 本发明是仅发出相关领域的方案。
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10.发明授权Address range comparator for detection of multi-size memory accesses with data matching qualification and full or partial overlap 有权地址范围比较器，用于检测具有数据匹配限定和全部或部分重叠的多尺寸存储器访问公开(公告)号：US08655637B2
公开(公告)日：2014-02-18
申请号：US11566772
申请日：2006-12-05
申请人： Jose L. Flores , Lewis Nardini , Maria B. H. Gill
发明人： Jose L. Flores , Lewis Nardini , Maria B. H. Gill
IPC分类号： G06F9/455
CPC分类号： G06F11/3648 , G01R31/31703 , G01R31/31705 , G06F11/3656
摘要： An memory access address comparator includes two comparators comparing an input memory access address with respective reference addresses. The comparators produce a match indication on selectable criteria, such as address size, full or partial overlap, greater than, less than, equal to, not equal to, less than or equal to, and greater than or equal to, and can be selectively chained. Input multiplexers permit memory access address bus selection. The comparator output may be selectively dependent upon corresponding data matches. The reference addresses, comparison data and control functions are enabled via central processing unit accessible memory mapped registers.
摘要翻译： 存储器访问地址比较器包括将输入存储器访问地址与相应的参考地址进行比较的两个比较器。 比较器根据可选择的标准产生匹配指示，例如地址大小，全部或部分重叠，大于，小于，等于，不等于，小于等于并且大于或等于，并且可以是选择性地 链接。 输入多路复用器允许存储器访问地址总线选择。 比较器输出可以选择性地依赖于相应的数据匹配。 参考地址，比较数据和控制功能通过中央处理单元可访问存储器映射寄存器使能。
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