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公开(公告)号:US10652536B2
公开(公告)日:2020-05-12
申请号:US16417509
申请日:2019-05-20
Inventor: Chong Soon Lim , Hai Wei Sun , Sughosh Pavan Shashidhar , Han Boon Teo , Ru Ling Liao , Takahiro Nishi , Tadamasa Toma
IPC: H04N19/119 , H04N19/176 , H04N19/50 , H04N19/60
Abstract: An encoder according to one aspect of the present disclosure encodes a block of an image, and includes a processor and memory connected to the processor. Using the memory, the processor partitions a block into a plurality of sub blocks and encodes a sub block included in the plurality of sub blocks in an encoding process including at least a transform process or a prediction process. The block is partitioned using a multiple partition including at least three odd-numbered child nodes and each of a width and a height of each of the plurality of sub blocks is a power of two.
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公开(公告)号:US10327007B2
公开(公告)日:2019-06-18
申请号:US14578111
申请日:2014-12-19
Inventor: Kengo Terada , Hisao Sasai , Tadamasa Toma , Noritaka Iguchi , Yui Koashi
IPC: H04N7/12 , H04N11/02 , H04N11/04 , H04N19/52 , H04N19/436
Abstract: There is provided a decoding method for decoding an image, the method including: transmitting a request for an image to an external apparatus; receiving a coded signal corresponding to the image that has been requested and including a first signal and a second signal, and storing the coded signal in a storage; decoding the first signal and the second signal included in the coded signal; and displaying a first image decoded from the first signal in a first region of a screen, and displaying a second image decoded from the second signal in a second region of the screen. The second signal is a signal that has been selected by the external apparatus for a decoding apparatus from among a plurality of candidates for the second signal.
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公开(公告)号:US10277931B2
公开(公告)日:2019-04-30
申请号:US15044203
申请日:2016-02-16
Inventor: Noritaka Iguchi , Tadamasa Toma , Takahiro Nishi , Hisaya Katou
IPC: H04N21/462 , H04N21/8547 , H04N21/242 , H04N21/61 , H04N21/44 , H04N21/43 , H04H60/13 , H04H20/18
Abstract: According to one aspect of the present disclosure, a reception method in broadcast and broadband cooperation service, the reception method includes: receiving broadcast content transmitted through broadcast; receiving acquisition information through the broadcast, the acquisition information being information used to play back broadband content transmitted through broadband while the broadband content is synchronized with the received broadcast content, the acquisition information being information relating to acquisition of the broadband content; and acquiring the broadband content based on the received acquisition information. Therefore, the broadband content can properly be acquired in response to the reception of the broadcast content.
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公开(公告)号:US10070199B2
公开(公告)日:2018-09-04
申请号:US15063602
申请日:2016-03-08
Inventor: Noritaka Iguchi , Tadamasa Toma , Hisaya Katou
IPC: H04N21/643 , H04N21/8547 , H04N21/236 , H04N21/434 , H04N21/61
Abstract: A transmission method includes: generating one or more frames for content transfer, each of the frames containing one or more second transfer units, each of the second transfer units being placed at a head within each of the frames and containing one or more first transfer units, each of the first transfer units containing one or more Internet Protocol (IP) packets, each of the first transfer units positioned at a head within each of the frames containing reference clock information indicating time used for reproduction of the content that uses the IP packets in a reception apparatus; and transmitting the one or more frames by broadcast.
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公开(公告)号:US09992549B2
公开(公告)日:2018-06-05
申请号:US15075229
申请日:2016-03-21
Inventor: Noritaka Iguchi , Tadamasa Toma , Hisaya Katou
IPC: H04N21/8547 , H04N21/643 , H04L29/12 , H04L29/06 , H04N21/242 , H04N21/43 , H04N21/61 , H04N21/845 , H04L29/10 , H04J3/06
CPC classification number: H04N21/64322 , H04J3/0667 , H04L29/10 , H04L61/2007 , H04L69/04 , H04L69/22 , H04L69/28 , H04N21/242 , H04N21/4302 , H04N21/6125 , H04N21/6143 , H04N21/6175 , H04N21/6193 , H04N21/845 , H04N21/8547
Abstract: A transmission method includes: generating one or more transfer frames that each store one or more streams used for content transfer; and transmitting the one or more generated frames through broadcast, each of the one or more streams storing one or more second transfer units, each of the one or more second transfer units storing one or more first transfer units, and each of the one or more first transfer units storing one or more Internet Protocol (IP) packets. In at least one stream among the one or more streams, each of the first transfer units positioned at a head contains reference clock information indicating time used for reproduction of the content.
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公开(公告)号:US20250088684A1
公开(公告)日:2025-03-13
申请号:US18955001
申请日:2024-11-21
Inventor: Noritaka IGUCHI , Tadamasa Toma , Takahiro Nishi , Hisaya Katou
IPC: H04N21/242 , H04H20/18 , H04H60/13 , H04N21/43 , H04N21/44 , H04N21/462 , H04N21/61 , H04N21/8547
Abstract: According to one aspect of the present disclosure, a reception method in broadcast and broadband cooperation service, the reception method includes: receiving broadcast content transmitted through broadcast; receiving acquisition information through the broadcast, the acquisition information being information used to play back broadband content transmitted through broadband while the broadband content is synchronized with the received broadcast content, the acquisition information being information relating to acquisition of the broadband content; and acquiring the broadband content based on the received acquisition information. Therefore, the broadband content can properly be acquired in response to the reception of the broadcast content.
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公开(公告)号:US12244796B2
公开(公告)日:2025-03-04
申请号:US18510427
申请日:2023-11-15
Inventor: Ryuichi Kanoh , Takahiro Nishi , Tadamasa Toma , Kiyofumi Abe
IPC: H04N19/117 , H04N19/146 , H04N19/176
Abstract: A decoder comprises circuitry and memory. The circuitry, using the memory, in operation, determines a number of first pixels and a number of second pixels used in a deblocking filter process, wherein the first pixels are located at an upper side of a block boundary and the second pixels are located at a lower side of the block boundary, and performs the deblocking filter process on the block boundary. The number of the first pixels and the number of the second pixels are selected from among candidates, wherein the candidates include at least 4 and M larger than 4. Response to a location of the block boundary being a predetermined location, the number of the first pixels used in the deblocking filter process is limited to be 4.
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公开(公告)号:US12225220B2
公开(公告)日:2025-02-11
申请号:US17684657
申请日:2022-03-02
Inventor: Kiyofumi Abe , Takahiro Nishi , Tadamasa Toma , Yusuke Kato
IPC: H04N19/423 , H04N19/159 , H04N19/176 , H04N19/82
Abstract: An encoder includes circuitry and memory coupled to the circuitry. In operation, the circuitry determines one or more tiles included in a picture and one or more subpictures included in the picture, according to a constraint condition that each tile of the one or more tiles includes at least one subpicture of the one or more subpictures entirely and the each tile does not include another subpicture of the one or more subpictures partially.
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公开(公告)号:US12177438B2
公开(公告)日:2024-12-24
申请号:US18311064
申请日:2023-05-02
Inventor: Tadamasa Toma , Takahiro Nishi , Kiyofumi Abe , Yusuke Kato
IPC: H04N19/124 , H04N19/136 , H04N19/157 , H04N19/176 , H04N19/61
Abstract: An encoder includes circuitry and memory coupled to the circuitry. In operation, the circuitry: performs quantization on a plurality of transform coefficients of a current block to be encoded, using a quantization matrix when orthogonal transform is performed on the current block and secondary transform is not performed on the current block; and performs quantization on the plurality of transform coefficients of the current block without using the quantization matrix when orthogonal transform is not performed on the current block and when both orthogonal transform and secondary transform are performed on the current block.
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公开(公告)号:US12166983B2
公开(公告)日:2024-12-10
申请号:US18531574
申请日:2023-12-06
Inventor: Chong Soon Lim , Hai Wei Sun , Sughosh Pavan Shashidhar , Han Boon Teo , Ru Ling Liao , Takahiro Nishi , Tadamasa Toma
IPC: H04N19/119 , H04N19/157 , H04N19/159 , H04N19/176 , H04N19/196 , H04N19/463 , H04N19/96
Abstract: An image encoder/decoder includes circuitry and a memory coupled to the circuitry. When a geometry of a block of a picture satisfies a first condition, the circuitry splits the block of the picture into sub blocks having a first set of geometries. When the geometry of the block does not satisfy the first condition, the circuitry splits the block of the picture into sub blocks having a second set of geometries, the second set of geometries being different from the first set of geometries. The circuitry encodes/decodes the sub blocks of the block.
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