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公开(公告)号：US20240121384A1
公开(公告)日：2024-04-11
申请号：US18539753
申请日：2023-12-14
Inventor： Jing Ya LI , Ru Ling Liao , Chong Soon Lim , Han Boon Teo , Hai Wei Sun , Che Wei Kuo , Kiyofumi Abe , Takahiro Nishi , Tadamasa Toma
IPC: H04N19/105 , H04N19/136 , H04N19/159 , H04N19/176 , H04N19/52 , H04N19/80
CPC classification number: H04N19/105 , H04N19/136 , H04N19/159 , H04N19/176 , H04N19/52 , H04N19/80
Abstract: An encoder includes circuitry and memory connected to the circuitry. The circuitry: derives an absolute value of a sum of horizontal gradient values; derives, as a first parameter, the total sum of the absolute values of horizontal gradient values; derives, as a second parameter, the total sum of the absolute values of vertical gradient values; derives a horizontal-related pixel difference value; derives, as a third parameter, the total sum of the absolute values of horizontal-related pixel difference values; derives a vertical-related pixel difference value; derives, as a fourth parameter, the total sum of the absolute values of vertical-related pixel difference values; and generates a prediction image using the first to fourth parameters.
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公开(公告)号：US20240114134A1
公开(公告)日：2024-04-04
申请号：US18530032
申请日：2023-12-05
Inventor： Sughosh Pavan SHASHIDHAR , Hai Wei SUN , Chong Soon LIM , Ru Ling LIAO , Han Boon TEO , Jing Ya LI , Takahiro NISHI , Kiyofumi ABE , Ryuichi KANOH , Tadamasa TOMA
IPC: H04N19/119 , H04N19/176 , H04N19/184 , H04N19/60
CPC classification number: H04N19/119 , H04N19/176 , H04N19/184 , H04N19/60
Abstract: An encoder includes circuitry and a memory coupled to the circuitry. The circuitry, in operation, determines whether or not a ternary split process of splitting a block into three sub blocks in a first direction parallel to a first longer side of the block is allowed by comparing a size of a second shorter side of the block to a minimum threshold value. The circuitry, responsive to the ternary split process being allowed, writes, into a bitstream, a split direction parameter indicative of a splitting direction. The circuitry, in operation, splits the block into a plurality of sub blocks in a direction indicated by the split direction parameter; and encodes the plurality of sub blocks. The minimum threshold value corresponds to a minimum size supported in a transform process.
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公开(公告)号：US20240015322A1
公开(公告)日：2024-01-11
申请号：US18473027
申请日：2023-09-22
Inventor： Jing Ya LI , Chong Soon LIM , Sughosh Pavan SHASHIDHAR , Ru Ling LIAO , Hai Wei SUN , Han Boon TEO , Kiyofumi ABE , Tadamasa TOMA , Takahiro NISHI
IPC: H04N19/513 , H04N19/119 , H04N19/176 , H04N19/96
CPC classification number: H04N19/521 , H04N19/119 , H04N19/176 , H04N19/96
Abstract: An encoder includes circuitry and memory connected to the circuitry. In operation, the circuitry corrects a base motion vector using a correction value in a fixed direction; and encodes a current partition by using the corrected base motion vector corrected. The correction value is specified by an index indicating one of correction values included in a table. The table is selected from among a plurality of tables, wherein the correction values in one of the plurality of tables have different increments from the correction values in another one of the plurality of tables.
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公开(公告)号：US20240007644A1
公开(公告)日：2024-01-04
申请号：US18467531
申请日：2023-09-14
Inventor： Ru Ling LIAO , Chong Soon LIM , Hai Wei SUN , Han Boon TEO , Jing Ya LI , Kiyofumi ABE , Takahiro NISHI , Tadamasa TOMA
IPC: H04N19/137 , H04N19/159 , H04N19/176 , H04N19/105 , H04N19/132 , H04N19/119
CPC classification number: H04N19/137 , H04N19/159 , H04N19/176 , H04N19/105 , H04N19/132 , H04N19/119
Abstract: An image encoder or decoder includes circuitry and a memory coupled to the circuitry. The circuitry, in operation, predicts a first set of samples for a first partition of a current picture with one or more motion vectors including a first motion vector and predicts a second set of samples for a first portion of the first partition with one or more motion vectors from a second partition different from the first partition. The samples of the first set of samples of the first portion of the first partition and of the second set of samples of the first portion of the first partition are weighted. A motion vector for the first portion of the first partition is stored which is based on one or both of the first motion vector and the second motion vector. The first partition is encoded or decoded using at least the weighted samples of the first portion of the first partition.
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公开(公告)号：US20230345035A1
公开(公告)日：2023-10-26
申请号：US18217840
申请日：2023-07-03
Inventor： Jing Ya LI , Chong Soon LIM , Ru Ling LIAO , Han Boon TEO , Hai Wei SUN , Che Wei KUO , Kiyofumi ABE , Takahiro NISHI , Tadamasa TOMA
IPC: H04N19/513 , H04N19/139 , H04N19/159 , H04N19/176
CPC classification number: H04N19/513 , H04N19/139 , H04N19/159 , H04N19/176
Abstract: Provided is an encoder including circuitry and memory coupled to the circuitry. A prediction mode for a current block is an affine mode, and in operation, the circuitry: derives a base motion vector which is a motion vector to be used in a prediction process for the current block, and is a motion vector at an affine-mode control point in the current block; derives a first motion vector different from the base motion vector; derives a motion vector difference based on a difference between the base motion vector and the first motion vector; determines whether the motion vector difference is greater than a threshold; if so, modifies a second motion vector different from the base motion vector and the first motion vector, and if not, does not modify the second motion vector; and encodes the current block using the second motion vector modified or the second motion vector not modified.
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Patent Agency Ranking
公开(公告)号：US20230344996A1
公开(公告)日：2023-10-26
申请号：US18208380
申请日：2023-06-12
Inventor： Chong Soon LIM , Hai Wei SUN , Jing Ya LI , Han Boon TEO , Che-Wei KUO , Chu Tong WANG , Kiyofumi ABE , Takahiro NISHI , Tadamasa TOMA , Yusuke KATO
IPC: H04N19/117 , H04N19/132 , H04N19/169 , H04N19/82
CPC classification number: H04N19/117 , H04N19/132 , H04N19/188 , H04N19/82
Abstract: An encoder includes circuitry and memory coupled to the circuitry. In operation, the circuitry: encodes information for deriving a parameter into a header of a bitstream; filters reconstructed samples in a first image using a filtering process, to generate a second image; determines whether the parameter has a predefined value; encodes a third image using the second image when the parameter has the predefined value; and encodes the third image using the first image when the parameter does not have the predefined value.
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公开(公告)号：US20230276057A1
公开(公告)日：2023-08-31
申请号：US18118238
申请日：2023-03-07
Inventor： Kiyofumi ABE , Takahiro NISHI , Tadamasa TOMA , Ryuichi KANOH , Chong Soon LIM , Ru Ling LIAO , Hai Wei SUN , Sughosh Pavan SHASHIDHAR , Han Boon TEO , Jing Ya LI
IPC: H04N19/159 , H04N19/513 , H04N19/139 , H04N19/119
CPC classification number: H04N19/159 , H04N19/119 , H04N19/139 , H04N19/521
Abstract: An encoder encodes a video, and includes: circuitry; and memory coupled to the circuitry. Using the memory, the circuitry: obtains at least two items of prediction information for a first partition included in the video; derives at least one template from neighboring samples which neighbor the first partition; calculates at least two costs, using the at least one template and the at least two items of prediction information; using the at least two costs, (i) determines at least one splitting direction for the first partition or (ii) assigns one of the at least two items of prediction information to a second partition split from the first partition according to the splitting direction, and another thereof to a third partition split from the first partition according to the splitting direction; and encodes the first partition according to the splitting direction and the at least two items of prediction information.
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公开(公告)号：US20230118198A1
公开(公告)日：2023-04-20
申请号：US18066873
申请日：2022-12-15
Inventor： Kiyofumi ABE , Takahiro NISHI , Tadamasa TOMA , Ryuichi KANOH , Chong Soon LIM , Ru Ling LIAO , Hai Wei SUN , Sughosh Pavan SHASHIDHAR , Han Boon TEO , Jing Ya LI
IPC: H04N19/51 , H04N19/176 , H04N19/182
Abstract: An encoder includes circuitry and a memory coupled to the circuitry, wherein the circuitry, in operation, performs a partition process. The partition process includes calculating first values of a set of pixels between a first partition and a second partition in a current block, using a first motion vector for the first partition; calculating second values of the set of pixels, using a second motion vector for the second partition; and calculating third values of the set of pixels by weighting the first values and the second values. When a ratio of a width to a height of the current block is larger than 4 or a ratio of the height to the width of the current block is larger than 4, the circuitry disables the partition process.
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公开(公告)号：US20230115058A1
公开(公告)日：2023-04-13
申请号：US18071365
申请日：2022-11-29
Inventor： Jing Ya LI , Chong Soon LIM , Hai Wei SUN , Han Boon TEO , Che Wei KUO , Chu Tong WANG , Kiyofumi ABE , Takahiro Nishi , Tadamasa Toma , Yusuke KATO
IPC: H04N19/117 , H04N19/105 , H04N19/119 , H04N19/82 , H04N19/13 , H04N19/18 , H04N19/186 , H04N19/124
Abstract: An encoder includes circuitry and memory. The circuitry, in operation, generates a first coefficient value by applying a CCALF (cross component adaptive loop filtering) process to a first reconstructed image sample of a luma component. The circuitry generates a second coefficient value by applying an ALF (adaptive loop filtering) process to a second reconstructed image sample of a chroma component. The circuitry generates a third coefficient value by adding the first coefficient value to the second coefficient value, and encodes a third reconstructed image sample of the chroma component using the third coefficient value. In the CCALF process, in response to a coordinate of the second reconstructed image sample being (x, y), coordinates of the first reconstructed image samples are (2x, 2y−1), (2x−1, 2y), (2x, 2y), (2x+1, 2y), (2x−1, 2y+1), (2x, 2y+1), (2x+1, 2y+1), and (2x, 2y+2).
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公开(公告)号：US20220248011A1
公开(公告)日：2022-08-04
申请号：US17724179
申请日：2022-04-19
Inventor： Kiyofumi ABE , Takahiro NISHI , Tadamasa TOMA , Ryuichi KANOH , Chong Soon LIM , Ru Ling LIAO , Hai Wei SUN , Sughosh Pavan SHASHIDHAR , Han Boon TEO , Jing Ya LI
IPC: H04N19/119 , H04N19/176
Abstract: Provided is an encoder which includes circuitry and memory. The circuitry encodes an image block using the memory. In encoding the image block, the circuitry: obtains one or more size parameters related to a size of the image block; determines whether the one or more size parameters and one or more thresholds satisfy a determined relationship; encodes a split parameter when the one or more size parameters and the one or more thresholds are determined to satisfy the determined relationship, the split parameter indicating whether the image block is to be split into a plurality of partitions including a non-rectangular partition; and encodes the image block after splitting the image block into the plurality of partitions when the split parameter indicates that the image block is to be split into the plurality of partitions.
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