公开(公告)号：US6121093A

公开(公告)日：2000-09-19

申请号：US164446

申请日：1998-09-30

Applicant: Peng Cheng ,  Brian Doyle

Inventor： Peng Cheng ,  Brian Doyle

IPC: H01L21/28 ,  H01L21/336

CPC classification number: H01L29/6659 ,  H01L21/28132 ,  H01L29/66651 ,  H01L29/66659 ,  Y10S438/945

Abstract: A method of forming an asymmetric transistor and an asymmetric transistor. The method includes patterning a first spacer material and a second spacer material over a gate electrode material on a substrate with one side of the second spacer material adjacent to a first spacer material. The gate electrode material is patterned according to the first spacer material and the second material. Junction regions are formed in the substrate adjacent to the gate electrode material. One of the first spacer material and the second spacer material is then removed and the gate electrode material is patterned into a gate electrode according to the other of the first spacer and the second spacer material. Finally, second junction regions are formed in the substrate adjacent to gate electrode.

Abstract translation: 一种形成不对称晶体管和不对称晶体管的方法。 该方法包括在衬底上的栅极电极材料上形成第一间隔物材料和第二间隔物材料，其中第二间隔物材料的一侧与第一间隔物材料相邻。 根据第一间隔物材料和第二材料对栅电极材料进行图案化。 在与栅电极材料相邻的衬底中形成结区。 然后去除第一间隔物材料和第二间隔物材料中的一个，并且根据第一间隔物和第二间隔物材料中的另一个将栅电极材料图案化成栅电极。 最后，在与栅电极相邻的衬底中形成第二结区。

公开(公告)号：US5536684A

公开(公告)日：1996-07-16

申请号：US269440

申请日：1994-06-30

Applicant: M. Lawrence A. Dass ,  Peng Cheng ,  David B. Fraser

Inventor： M. Lawrence A. Dass ,  Peng Cheng ,  David B. Fraser

IPC: H01L21/225 ,  H01L21/285 ,  H01L21/441

CPC classification number: H01L21/28518 ,  H01L21/2257 ,  Y10S148/015 ,  Y10S148/035 ,  Y10S148/147

Abstract: A process for the formation of a planar epitaxial cobalt silicide and for the formation of shallow conformal junctions for use in semiconductor processing. A cobalt silicide and titanium nitride bilayer is formed. The titanium nitride layer is chemically removed. Ions with or without a dopant are then implanted into the cobalt silicide layer. During the ion implantation, at least a portion of the cobalt silicide layer is transformed into an amorphous cobalt silicon mixture while the non-amorphous portion remains single crystal. If the ion implantation contains dopants, then after the implantation is completed, both the amorphous and non-amorphous portions of the cobalt silicide layer contain the dopants. The substrate is then annealed in either an ambient comprising a nitrogen gas or in an oxidizing ambient. During the anneal, the amorphous portion of the silicon substrate recrystallizes into a single crystal cobalt silicide layer. If the cobalt silicide layer after the ion implantation contain dopants, then during the anneal the dopants are driven out of the cobalt silicide layer and diffuse into the silicon substrate to form a conformal shallow junction. The resulting structure can be used in the vertical integration of microelectronic devices. In other words, the resulting structure is suitable for growing selective epitaxial silicon, for growing epitaxial insulators, for processing devices above the silicide in that epitaxial silicon, and for processing devices with buried conductors.

Abstract translation: 用于形成平面外延钴硅化物并形成用于半导体处理的浅共形结的方法。 形成硅化钴和氮化钛双层。 化学去除氮化钛层。 然后将具有或不具有掺杂剂的离子注入到硅化钴层中。 在离子注入期间，将至少一部分硅化钴层转变为无定形钴硅混合物，而非非晶部分保持单晶。 如果离子注入包含掺杂剂，则在注入完成之后，硅化钴层的非晶态部分和非非晶部分均含有掺杂剂。 然后将衬底在包含氮气的环境中或在氧化环境中退火。 在退火期间，硅衬底的非晶部分再结晶成单晶硅化钴层。 如果离子注入后的硅化钴层含有掺杂剂，则在退火期间，掺杂剂被驱出钴硅化物层并扩散到硅衬底中以形成共形的浅结。 所得结构可用于微电子器件的垂直集成。 换句话说，所得结构适于生长选择性外延硅，用于生长外延绝缘体，用于在该外延硅中的硅化物上方处理器件，以及用于处理具有埋入导体的器件。