公开(公告)号：US11955533B2

公开(公告)日：2024-04-09

申请号：US17873380

申请日：2022-07-26

申请人： Applied Materials, Inc.

发明人： Sipeng Gu ,  Baonian Guo ,  Qintao Zhang ,  Wei Zou ,  Kyuha Shim

IPC分类号： H01L29/66 ,  H01L21/28 ,  H01L21/3215 ,  H01L21/3213 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

CPC分类号： H01L29/66545 ,  H01L21/28132 ,  H01L21/32155 ,  H01L29/66742 ,  H01L21/32139 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66553 ,  H01L29/78696

摘要： Approaches herein decrease nanosheet gate length variations by implanting a gate layer material with ions prior to etching. A method may include forming a dummy gate structure over a nanosheet stack, the dummy gate structure including a hardmask atop a gate material layer, and removing a portion of the hardmask to expose a first area and a second area of the gate material layer. The method may further include implanting the dummy gate structure to modify the first and second areas of the gate material layer, and etching the first and second areas of the gate material layer to form a treated layer along a sidewall of a third area of the gate material layer, wherein the third area is beneath the hardmask.

公开(公告)号：US20180247828A1

公开(公告)日：2018-08-30

申请号：US15968285

申请日：2018-05-01

申请人： LAM RESEARCH CORPORATION

发明人： Jae Ho LEE ,  Changwoo LEE ,  Phil FRIDDLE ,  Stefan SCHMITZ ,  Naveed ANSARI ,  Michael GOSS ,  Noel SUN

IPC分类号： H01L21/311

CPC分类号： H01L21/31144 ,  H01J37/32366 ,  H01J2237/334 ,  H01L21/02164 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/0332 ,  H01L21/0334 ,  H01L21/0337 ,  H01L21/28132 ,  H01L21/28141 ,  H01L21/283 ,  H01L21/3086 ,  H01L21/31116

摘要： A system for performing a sidewall image transfer process includes a substrate processing chamber configured to process a substrate including a mandrel layer. A controller is configured to control the substrate processing chamber to, without the substrate being removed from the within the substrate processing chamber, etch the mandrel layer, subsequent to etching the mandrel layer, deposit a thin spacer layer on upper surfaces of the plurality of mandrels, sidewalls of the plurality of mandrels, and portions of the substrate between the sidewalls, subsequent to depositing the thin spacer layer, etch the thin spacer layer to remove the thin spacer layer such that only the thin spacer layer formed on the sidewalls of the plurality of mandrels remains and, subsequent to etching the thin spacer layer, etch the mandrels such that only the thin spacer layer formed on the sidewalls of the plurality of mandrels remains on the substrate.

公开(公告)号：US20180174846A1

公开(公告)日：2018-06-21

申请号：US15380329

申请日：2016-12-15

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Shiang-Bau WANG ,  Victor Y. LU

IPC分类号： H01L21/28 ,  H01L29/78 ,  H01L29/66 ,  H01L29/08

CPC分类号： H01L21/28132 ,  H01L29/0847 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/785

摘要： The present disclosure provides a semiconductor structure, including a semiconductor fin, a metal gate over the semiconductor fin, and a sidewall spacer composed of low-k dielectric surrounding opposing sidewalls of the metal gate. A portion of the sidewall spacer comprises a tapered profile with a greater separation of the opposing sidewalls toward a top portion and a narrower separation of the opposing sidewalls toward a bottom portion of the sidewall spacer. The present disclosure also provides a method of manufacturing a semiconductor device. The method includes forming a polysilicon stripe over a semiconductor fin, forming a nitride sidewall spacer surrounding a long side of the polysilicon stripe, forming a raised source/drain region in the semiconductor fin, and forming a carbonitride etch stop layer surrounding the nitride sidewall spacer.

公开(公告)号：US20180083120A1

公开(公告)日：2018-03-22

申请号：US15595240

申请日：2017-05-15

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Ruqiang Bao ,  Dechao Guo ,  Zuoguang Liu

IPC分类号： H01L29/66

CPC分类号： H01L21/823475 ,  H01L21/0217 ,  H01L21/02247 ,  H01L21/28132 ,  H01L21/32133 ,  H01L21/76802 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823437 ,  H01L23/5226 ,  H01L23/5286 ,  H01L27/0886 ,  H01L29/41791 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795

摘要： Methods of forming a semiconductor device include laterally etching a dummy gate to recess the dummy gate underneath a spacer layer, such that the spacer layer overhangs the dummy gate. A sidewall of the dummy gate is nitridized. The dummy gate is etched away without removing the nitridized sidewall.

公开(公告)号：US20180069012A1

公开(公告)日：2018-03-08

申请号：US15811426

申请日：2017-11-13

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Jhon Jhy LIAW

IPC分类号： H01L27/11 ,  H01L27/02 ,  H01L21/8234 ,  H01L21/311 ,  H01L21/768 ,  H01L29/66 ,  H01L29/417 ,  H01L21/027 ,  H01L21/28

CPC分类号： H01L27/1104 ,  H01L21/0274 ,  H01L21/28132 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823821 ,  H01L27/0207 ,  H01L29/41791 ,  H01L29/66545

摘要： In a method of manufacturing an SRAM device, an insulating layer is formed over a substrate. First dummy patterns are formed over the insulating layer. Sidewall spacer layers, as second dummy patterns, are formed on sidewalls of the first dummy patterns. The first dummy patterns are removed, thereby leaving the second dummy patterns over the insulating layer. After removing the first dummy patterns, the second dummy patterns are divided. A mask layer is formed over the insulating layer and between the divided second dummy patterns. After forming the mask layer, the divided second dummy patterns are removed, thereby forming a hard mask layer having openings that correspond to the patterned second dummy patterns. The insulating layer is formed by using the hard mask layer as an etching mask, thereby forming via openings in the insulating layer. A conductive material is filled in the via openings, thereby forming contact bars.

公开(公告)号：US09831334B2

公开(公告)日：2017-11-28

申请号：US15198526

申请日：2016-06-30

申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

发明人： Gary H. Loechelt

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/40 ,  H01L29/66 ,  H01L21/28 ,  H01L29/423

CPC分类号： H01L29/7809 ,  H01L21/28132 ,  H01L29/063 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/42376 ,  H01L29/66712 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7802 ,  H01L29/7812 ,  H01L29/7813

摘要： An electronic device can include a semiconductor layer, an insulating layer overlying the semiconductor layer, and a conductive electrode. In an embodiment, a first conductive electrode member overlies the insulating layer, and a second conductive electrode member overlies and is spaced apart from the semiconductor layer. The second conductive electrode member has a first end and a second end opposite the first end, wherein each of the semiconductor layer and the first conductive electrode member are closer to the first end of the second conductive electrode member than to the second end of the second conductive electrode member. In another embodiment, the conductive electrode can be substantially L-shaped. In a further embodiment, a process can include forming the first and second conductive electrode members such that they abut each other. The second conductive electrode member can have the shape of a sidewall spacer.

公开(公告)号：US20170221700A1

公开(公告)日：2017-08-03

申请号：US15492034

申请日：2017-04-20

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shich-Chang Suen ,  Li-Chieh Wu ,  Chi-Jen Liu ,  He Hui Peng ,  Liang-Guang Chen ,  Yung-Chung Chen

IPC分类号： H01L21/02 ,  H01L21/288 ,  H01L21/768 ,  H01L21/311

CPC分类号： H01L21/02068 ,  H01L21/02063 ,  H01L21/0234 ,  H01L21/28079 ,  H01L21/28132 ,  H01L21/288 ,  H01L21/31105 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76804 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76895 ,  H01L29/401 ,  H01L29/66545

摘要： The present disclosure provides a method for forming an integrated circuit (IC) structure. The method includes providing a metal gate (MG), an etch stop layer (ESL) formed on the MG, and a dielectric layer formed on the ESL. The method further includes etching the ESL and the dielectric layer to form a trench. A surface of the MG exposed in the trench is oxidized to form a first oxide layer on the MG. The method further includes removing the first oxide layer using a H3PO4 solution.

公开(公告)号：US20170125539A1

公开(公告)日：2017-05-04

申请号：US15233315

申请日：2016-08-10

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

发明人： Kangguo Cheng ,  Ruilong Xie ,  Tenko Yamashita

IPC分类号： H01L29/49 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423

CPC分类号： H01L29/4991 ,  H01L21/28114 ,  H01L21/28132 ,  H01L21/283 ,  H01L21/31 ,  H01L21/31111 ,  H01L21/764 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76879 ,  H01L21/823468 ,  H01L21/823864 ,  H01L23/5226 ,  H01L29/401 ,  H01L29/41775 ,  H01L29/41791 ,  H01L29/42376 ,  H01L29/515 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

摘要： A semiconductor device that includes a gate structure on a channel region of a semiconductor device. Source and drain regions may be present on opposing sides of the channel region. The semiconductor device may further include a composite gate sidewall spacer present on a sidewall of the gate structure. The composite gate sidewall spacer may include a first composition portion having an air gap encapsulated therein, and a second composition portion that is entirely solid and present atop the first composition portion.

公开(公告)号：US20170076957A1

公开(公告)日：2017-03-16

申请号：US14851768

申请日：2015-09-11

申请人： LAM RESEARCH CORPORATION

发明人： Jae Ho Lee ,  Changwoo Lee ,  Phil Friddle ,  Stefan Schmitz ,  Naveed Ansari ,  Michael Goss ,  Noel Sun

IPC分类号： H01L21/311 ,  H01J37/32 ,  H01L21/283 ,  H01L21/033 ,  H01L21/02

CPC分类号： H01L21/31144 ,  H01J37/32366 ,  H01J2237/334 ,  H01L21/02164 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/0332 ,  H01L21/0334 ,  H01L21/0337 ,  H01L21/28132 ,  H01L21/28141 ,  H01L21/283 ,  H01L21/3086 ,  H01L21/31116

摘要： A method of performing a sidewall image transfer (SIT) process includes arranging a substrate within a substrate processing chamber, wherein the substrate includes a mandrel layer formed on the substrate and etching the mandrel layer to form a plurality of mandrels. The method further includes, without removing the substrate from within the substrate processing chamber and subsequent to etching the mandrel layer, depositing a thin spacer layer such that the thin spacer layer is formed on upper surfaces of the plurality of mandrels, sidewalls of the plurality of mandrels, and portions of the substrate between the sidewalls of the plurality of mandrels, subsequent to depositing the thin spacer layer, etching the thin spacer layer to remove the thin spacer layer from the upper surfaces of the mandrels and the portions of the substrate between the sidewalls of the plurality of mandrels such that only the thin spacer layer formed on the sidewalls of the plurality of mandrels remains, and, subsequent to etching the thin spacer layer from the upper surfaces of the mandrels and the portions of the substrate between the sidewalls of the plurality of mandrels, etching the plurality of mandrels to remove the plurality of mandrels from the substrate such that only the thin spacer layer formed on the sidewalls of the plurality of mandrels remains on the substrate.

摘要翻译： 执行侧壁图像转印（SIT）处理的方法包括在衬底处理室内布置衬底，其中衬底包括形成在衬底上的心轴层并蚀刻心轴层以形成多个心轴。 所述方法还包括：在不从所述衬底处理室内移除所述衬底并且在蚀刻所述心轴层之后，沉积薄间隔层，使得所述薄间隔层形成在所述多个心轴的上表面上， 心轴，以及在多个心轴的侧壁之间的衬底的部分，在沉积薄间隔层之后，蚀刻薄间隔层以从芯轴的上表面和衬垫的部分之间移除薄间隔层 多个心轴的侧壁使得只有形成在多个心轴的侧壁上的薄间隔层保留，并且在从所述心轴的上表面和衬底的部分在侧壁之间蚀刻薄间隔层之后， 多个心轴，蚀刻多个心轴以从衬底移除多个心轴使得 只有形成在多个心轴的侧壁上的薄间隔层保留在基底上。

公开(公告)号：US20170053805A1

公开(公告)日：2017-02-23

申请号：US15267357

申请日：2016-09-16

申请人： International Business Machines Corporation

发明人： Kangguo Cheng ,  Pouya Hashemi ,  Shogo Mochizuki ,  Alexander Reznicek

IPC分类号： H01L21/28 ,  H01L29/66

CPC分类号： H01L21/28132 ,  H01L21/28035 ,  H01L21/28123 ,  H01L21/32139 ,  H01L27/0207 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/4916 ,  H01L29/66545 ,  H01L29/6656

摘要： A method of making a semiconductor device includes forming a gate covered by a hard mask over a substrate; disposing a mask over the gate and the hard mask; patterning the mask to expose a portion of the gate and the hard mask; cutting the gate and hard mask to form two shorter gates, each of the two shorter gates having an exposed end portion; undercutting the exposed end portion of at least one of the two shorter gates to form an overhanging hard mask portion over the exposed end portion; and forming spacers along a gate sidewall and beneath the overhanging hard mask portion.

摘要翻译： 一种制造半导体器件的方法包括在衬底上形成由硬掩模覆盖的栅极; 在门和硬掩模上设置掩模; 图案化掩模以暴露栅极和硬掩模的一部分; 切割门和硬掩模以形成两个较短的门，两个较短的门中的每一个具有暴露的端部; 底切所述两个较短浇口中的至少一个的暴露端部，以在所述暴露的端部上方形成伸出的硬掩模部分; 以及沿着浇口侧壁并在突出的硬掩模部分之下形成间隔物。