公开(公告)号：US5821773A

公开(公告)日：1998-10-13

申请号：US524698

申请日：1995-09-06

申请人： Kevin A. Norman ,  Rakesh H. Patel ,  Stephen P. Sample ,  Michael R. Butts

发明人： Kevin A. Norman ,  Rakesh H. Patel ,  Stephen P. Sample ,  Michael R. Butts

IPC分类号： H03K19/173 ,  H03K19/177 ,  H03K7/38 ,  H03K19/00

CPC分类号： H03K19/17728 ,  H03K19/1737

摘要： A logic element for a programmable logic device. The logic element includes a look-up table (400) for implementing logical functions, a programmable delay block (415), a storage block (430) configurable as a latch or a flip-flop, and a diagnostic shadow latch (435). A plurality of inputs (410) to the logic element and complements of these inputs are available to control the secondary functions of the storage block (430).

摘要翻译： 可编程逻辑器件的逻辑元件。 逻辑元件包括用于实现逻辑功能的查找表（400），可编程延迟块（415），可配置为锁存器或触发器的存储块（430）和诊断阴影锁存器（435）。 逻辑元件的多个输入（410）和这些输入的补码可用于控制存储块（430）的辅助功能。

公开(公告)号：US5764079A

公开(公告)日：1998-06-09

申请号：US615342

申请日：1996-03-11

申请人： Rakesh H. Patel ,  Kevin A. Norman

发明人： Rakesh H. Patel ,  Kevin A. Norman

IPC分类号： G01R31/3185 ,  G06F17/50 ,  G11C7/10 ,  H03K19/177 ,  G01R31/3177

CPC分类号： G06F17/5027 ,  G01R31/318516 ,  G01R31/318536 ,  G11C29/48 ,  G11C7/1006 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17744 ,  H03K19/1776 ,  H03K19/17764

摘要： A programmable logic device (PLD) that provides the capability to observe and control the logic state of buried internal nodes is disclosed. The PLD provides shadow storage units for internal nodes such as logic element registers, memory cells, and I/O registers. A sample/load data path includes bidirectional data buses and shift register that facilitate the sampling of internal nodes for observing their logic states, and loading of internal nodes for controlling their logic states.

公开(公告)号：US5483178A

公开(公告)日：1996-01-09

申请号：US207012

申请日：1994-03-04

申请人： John C. Costello ,  Rakesh H. Patel

发明人： John C. Costello ,  Rakesh H. Patel

IPC分类号： H03K19/173 ,  H03K19/177

CPC分类号： H03K19/1737

摘要： A programmable logic device is provided that contains a plurality of logic array blocks arranged in rows and columns. The logic array blocks are interconnected with horizontal conductors in each row and vertical conductors in each column. The logic array blocks and the interconnections between conductors are configured using programmable logic. Some of the programmable logic is used to selectively connect logic array block input terminals to the horizontal conductors. Additional logic in each column is used to selectively connect the horizontal conductors to either logic array block output terminals from the same column or logic array block output terminals from an adjacent column. The additional logic prevents certain interconnection pathways from being blocked and increases the overall flexibility of the interconnection scheme of the programmable logic device, thereby improving device performance.

摘要翻译： 提供了一种可编程逻辑器件，其包含以行和列排列的多个逻辑阵列块。 逻辑阵列块与每行中的水平导体和每列中的垂直导体互连。 逻辑阵列块和导体之间的互连使用可编程逻辑进行配置。 一些可编程逻辑用于将逻辑阵列块输入端子选择性地连接到水平导体。 每列中的附加逻辑用于选择性地将水平导体连接到来自相邻列的相同列或逻辑阵列块输出端子的逻辑阵列块输出端子。 附加逻辑防止某些互连通路被阻塞，并增加可编程逻辑器件的互连方案的总体灵活性，从而提高器件性能。