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公开(公告)号：US20110317712A1
公开(公告)日：2011-12-29
申请号：US12823689
申请日：2010-06-25
CPC分类号： H04L49/9047
摘要： A method includes receiving a plurality of packets at an integrated processor block of a network on a chip device. The plurality of packets includes a first packet that includes an indication of a start of data associated with a pixel shader application. The method includes recovering the data from the plurality of packets. The method also includes storing the recovered data in a dedicated packet collection memory within the network on the chip device. The method further includes retaining the data stored in the dedicated packet collection memory during an interruption event. Upon completion of the interruption event, the method includes copying packets stored in the dedicated packet collection memory prior to the interruption event to an inbox of the network on the chip device for processing.
摘要翻译： 一种方法包括在芯片设备上的网络的集成处理器块处接收多个分组。 多个分组包括包括与像素着色器应用相关联的数据开始的指示的第一分组。 该方法包括从多个分组中恢复数据。 该方法还包括将恢复的数据存储在芯片设备上的网络内的专用分组收集存储器中。 该方法还包括在中断事件期间保留存储在专用分组收集存储器中的数据。 在中断事件完成时，该方法包括在中断事件之前将存储在专用分组收集存储器中的分组复制到芯片装置上的网络的收件箱进行处理。
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92.发明申请Software Trace Collection and Analysis Utilizing Direct Interthread Communication On A Network On Chip 审中-公开软件跟踪收集和分析利用网络上的直接间接通信公开(公告)号：US20110289485A1
公开(公告)日：2011-11-24
申请号：US12784533
申请日：2010-05-21
CPC分类号： G06F11/3636
摘要： Collecting and analyzing trace data while in a software debug mode through direct interthread communication (‘DITC’) on a network on chip (‘NOC’), the NOC including integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controllers, with each IP block adapted to a router through a memory communications controller and a network interface controller, where each memory communications controller controlling communications between an IP block and memory, and each network interface controller controlling inter-IP block communications through routers, including enabling the collection of software debug information in a selected set of IP blocks distributed through the NOC, each IP block within the selected set of IP blocks having a set of trace data; collecting software debugging information via the set of trace data; communicating the set of trace data to a destination repository; and analyzing the set of trace data at the destination repository.
摘要翻译： 在软件调试模式下，通过芯片上的直接通讯（DITC）（“NOC”）收集和分析跟踪数据，NOC包括集成处理器（IP）块，路由器，存储器通信控制器和 网络接口控制器，每个IP块通过存储器通信控制器和网络接口控制器适应于路由器，其中每个存储器通信控制器控制IP块和存储器之间的通信，以及每个网络接口控制器控制通过路由器进行IP间块通信 包括能够在通过NOC分配的所选择的一组IP块中收集软件调试信息，所选择的一组IP块中的每个IP块具有一组跟踪数据; 通过一组跟踪数据收集软件调试信息; 将该组跟踪数据传送到目的地存储库; 并分析目标存储库中的一组跟踪数据。
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公开(公告)号：US07992043B2
公开(公告)日：2011-08-02
申请号：US12255837
申请日：2008-10-22
IPC分类号： G06F11/00
CPC分类号： G06F11/362
摘要： A breakpoint packet is dispatched to a Network On A Chip (NOC). The breakpoint packet instructs one or more specified nodes on the NOC to place the specified nodes, or a core or hardware thread within a specified node, to execute in “single step” mode, in order to enable a debugging of a work packet that is dispatched to the specific node.
摘要翻译： 断点数据包被分派到片上网络（NOC）。 断点包指示NOC上的一个或多个指定节点将指定的节点或指定节点内的核心或硬件线程放置在“单步”模式下执行，以便能够调试工作包 调度到特定节点。
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公开(公告)号：US20100238169A1
公开(公告)日：2010-09-23
申请号：US12407398
申请日：2009-03-19
IPC分类号： G06T15/40
摘要： A circuit arrangement, program product and circuit arrangement utilize a textured bounding volume to reduce the overhead associated with generating and using an Accelerated Data Structure (ADS) in connection with physical rendering. In particular, a subset of the primitives in a scene may be mapped to surfaces of a bounding volume to generate textures on such surfaces that can be used during physical rendering. By doing so, the primitives that are mapped to the bounding volume surfaces may be omitted from the ADS to reduce the processing overhead associated with both generating the ADS and using the ADS during physical rendering, and furthermore, in many instances the size of the ADS may be reduced, thus reducing the memory footprint of the ADS, and often improving cache hit rates and reducing memory bandwidth.
摘要翻译： 电路布置，程序产品和电路布置利用纹理边界体积来减少与生成和使用结合物理渲染的加速数据结构（ADS）相关联的开销。 特别地，场景中的图元的子集可被映射到边界体积的表面，以在物理渲染期间使用的这些表面上生成纹理。 通过这样做，可以从ADS中省略映射到边界体积表面的原语，以减少在物理渲染期间生成ADS和使用ADS相关联的处理开销，此外，在许多情况下，ADS的大小 可以减少，从而减少ADS的内存占用，并且经常提高缓存命中率并减少内存带宽。
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95.发明申请SINGLE STEP MODE IN A SOFTWARE PIPELINE WITHIN A HIGHLY THREADED NETWORK ON A CHIP MICROPROCESSOR 失效芯片微处理器中的高度线性化网络中的软件管道中的单步模式公开(公告)号：US20100191940A1
公开(公告)日：2010-07-29
申请号：US12358776
申请日：2009-01-23
IPC分类号： G06F9/32
CPC分类号： G06F9/3844 , G06F9/30174 , G06F9/3806 , G06F11/3636 , G06F11/3648
摘要： A hardware thread is selectively forced to single step the execution of software instructions from a work packet granule. A “single step” packet is associated with a work packet granule. The work packet granule, with the associated “single step” packet, is dispatched as an appended work packet granule to a preselected hardware thread in a processor core, which, in one embodiment, is located at a node in a Network On a Chip (NOC). The work packet granule then executes in a single step mode until completion.
摘要翻译： 有选择地强制硬件线程从工作包颗粒单步执行软件指令。 “单步”包与工作包颗粒相关联。 具有相关联的“单步”分组的工作分组粒子被作为附加的工作分组粒子被分派到处理器核心中的预选硬件线程，在一个实施例中，其在一个实施例中位于网络片上（ NOC）。 工作包颗粒然后以单步模式执行直到完成。
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公开(公告)号：US20100188402A1
公开(公告)日：2010-07-29
申请号：US12360989
申请日：2009-01-28
IPC分类号： G06T15/50
CPC分类号： G06T15/06
摘要： A method, system and computer program product for managing secondary rays during ray-tracing are presented. A non-visible unidirectional ray tracing object logically surrounds a user-selected virtual object in a computer generated illustration. This unidirectional ray tracing object prevents secondary tracing rays from emanating from the user-selected virtual object during ray tracing.
摘要翻译： 提出了一种在射线跟踪期间管理二次射线的方法，系统和计算机程序产品。 在计算机生成的图示中，不可见的单向光线跟踪对象在逻辑上围绕用户选择的虚拟对象。 这种单向光线跟踪对象可防止在光线跟踪期间从用户选择的虚拟对象发出辅助跟踪光线。
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公开(公告)号：US20090125703A1
公开(公告)日：2009-05-14
申请号：US11937579
申请日：2007-11-09
CPC分类号： G06F9/461 , G06F15/7825
摘要： Data processing on a network on chip (‘NOC’) that includes integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controllers, with each IP block adapted to a router through a memory communications controller and a network interface controller, with each IP block also adapted to the network by a low latency, high bandwidth application messaging interconnect comprising an inbox and an outbox, each IP block also including a stack normally used for context switching, the stack access slower than the outbox access, and each IP block further including a processor supporting a plurality of threads of execution, the processor configured to save, upon a context switch, a context of a current thread of execution in memory locations in a memory array in the outbox instead of the stack and lock the memory locations in which the context was saved.
摘要翻译： 包括集成处理器（“IP”）块，路由器，存储器通信控制器和网络接口控制器的片上网络（“NOC”）上的数据处理，每个IP块通过存储器通信控制器和网络适配于路由器 接口控制器，每个IP块还通过包含收件箱和发件箱的低延迟，高带宽应用消息互连来适应网络，每个IP块还包括通常用于上下文切换的堆栈，堆栈访问比发送端口访问慢 并且每个IP块还包括支持多个执行线程的处理器，所述处理器被配置为在上下文切换时将所述执行的当前线程的上下文保存在所述发件箱中的存储器阵列中的存储器位置中，而不是所述堆栈 并锁定保存上下文的内存位置。
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98.发明授权Vector register file caching of context data structure for maintaining state data in a multithreaded image processing pipeline 有权用于在多线程图像处理管道中维护状态数据的上下文数据结构的向量寄存器文件缓存公开(公告)号：US08836709B2
公开(公告)日：2014-09-16
申请号：US13212418
申请日：2011-08-18
摘要： Frequently accessed state data used in a multithreaded graphics processing architecture is cached within a vector register file of a processing unit to optimize accesses to the state data and minimize memory bus utilization associated therewith. A processing unit may include a fixed point execution unit as well as a vector floating point execution unit, and a vector register file utilized by the vector floating point execution unit may be used to cache state data used by the fixed point execution unit and transferred as needed into the general purpose registers accessible by the fixed point execution unit, thereby reducing the need to repeatedly retrieve and write back the state data from and to an L1 or lower level cache accessed by the fixed point execution unit.
摘要翻译： 在多线程图形处理架构中使用的经常访问的状态数据被缓存在处理单元的向量寄存器文件中，以优化对状态数据的访问并最小化与其相关联的存储器总线利用。 处理单元可以包括固定点执行单元以及向量浮点执行单元，并且向量浮点执行单元使用的向量寄存器文件可用于对由固定点执行单元使用的状态数据进行缓存并转移为 需要进入由固定点执行单元访问的通用寄存器，从而减少了从固定点执行单元访问的L1或更低级高速缓存重复检索和回写状态数据的需要。
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99.发明授权Multithreaded software rendering pipeline with dynamic performance-based reallocation of raster threads 失效多线程软件渲染管道与基于动态性能的光栅线程重新分配公开(公告)号：US08587596B2
公开(公告)日：2013-11-19
申请号：US12824727
申请日：2010-06-28
IPC分类号： G06F15/80
CPC分类号： G06T1/20
摘要： A multithreaded rendering software pipeline architecture dynamically reallocates regions of an image space to raster threads based upon performance data collected by the raster threads. The reallocation of the regions typically includes resizing the regions assigned to particular raster threads and/or reassigning regions to different raster threads to better balance the relative workloads of the raster threads.
摘要翻译： 多线程渲染软件流水线架构基于栅格线程收集的性能数据，将图像空间的区域动态重新分配给栅格线程。 区域的重新分配通常包括调整分配给特定光栅线程的区域和/或重新分配区域到不同的光栅线程，以更好地平衡光栅线程的相对工作负载。
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公开(公告)号：US08413166B2
公开(公告)日：2013-04-02
申请号：US13212403
申请日：2011-08-18
IPC分类号： G06F3/00
CPC分类号： G06T1/20 , A63F2300/203 , A63F2300/64 , G06F9/544
摘要： A circuit arrangement and method implement impulse propagation in a multithreaded physics engine by assigning ownership of objects in a scene to individual threads and propagating impulses between objects that are in contact with one another by passing inter-thread impulse messages between the threads that own the contacting objects, while locally propagating impulses through objects using the threads to which such objects are assigned.
摘要翻译： 电路布置和方法通过将场景中的对象的所有权分配给单独的线程并且在彼此接触的对象之间传播脉冲来实现多线程物理引擎中的脉冲传播，所述对象通过在拥有所述接触的线程之间传递线间脉冲消息 对象，同时通过使用分配了这些对象的线程的对象来本地传播脉冲。
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