公开(公告)号：US06848071B2

公开(公告)日：2005-01-25

申请号：US10061521

申请日：2002-01-31

申请人： Shailender Chaudhry ,  Marc Tremblay

发明人： Shailender Chaudhry ,  Marc Tremblay

IPC分类号： G06F11/08 ,  G06F11/10 ,  G11C11/413 ,  G11C11/419 ,  G11C29/00

CPC分类号： G06F11/1064

摘要： One embodiment of the present invention provides a system that updates an error-correcting code for a line when only a portion of the line is updated during a store operation. The system operates by receiving the store operation, wherein the store operation includes new data to be stored to the portion of the line, as well as an address of the portion of the line. Next, the system reads old data for the portion of the line from the address, and then stores the new data to the portion of the line at the address. The system also updates the existing error-correcting code for the line to reflect the new data. This involves calculating a new error-correcting code for the line from the existing error-correcting code, the old data and the new data. The system then replaces the existing error-correcting code with the new error-correcting code.

摘要翻译： 本发明的一个实施例提供一种系统，当在存储操作期间仅更新线路的一部分时，更新线路的纠错码。 该系统通过接收存储操作进行操作，其中存储操作包括要存储到该行的该部分的新数据以及该行的该部分的地址。 接下来，系统从该地址读取该行的一部分的旧数据，然后将该新数据存储到该地址的该行的部分。 该系统还更新了该行的现有纠错码以反映新数据。 这涉及从现有纠错码，旧数据和新数据中计算出一条新的纠错码。 然后系统用新的纠错码代替现有的纠错码。

公开(公告)号：US06754775B2

公开(公告)日：2004-06-22

申请号：US10161794

申请日：2002-06-04

申请人： Shailender Chaudhry ,  Marc Tremblay

发明人： Shailender Chaudhry ,  Marc Tremblay

IPC分类号： G06F1200

CPC分类号： G06F12/0859 ,  G06F12/0813

摘要： One embodiment of the present invention provides a system that facilitates flow control to support pipelined accesses to a cache memory. When an access to the cache memory generates a miss, the system increments a number of outstanding misses that are currently in process for a set in the cache to which the miss is directed. If the number of outstanding misses is greater than or equal to a threshold value, the system stalls generation of subsequent accesses to the cache memory until the number of outstanding misses for each set in the cache memory falls below the threshold value. Upon receiving a cache line from a memory subsystem in response to an outstanding miss, the system identifies a set that the outstanding miss is directed to. The system then installs the cache line in an entry associated with the set. The system also decrements a number of outstanding misses that are currently in process for the set. If the number of outstanding misses falls below the threshold value as a result of decrementing, and if no other set has a number of outstanding misses that is greater than or equal to the threshold value, the system removes the stall condition so that subsequent accesses can be generated for the cache memory.

摘要翻译： 本发明的一个实施例提供了一种便于流控制以支持对高速缓存存储器的流水线访问的系统。 当访问高速缓冲存储器产生未命中时，系统会为未命中的高速缓存中的集合当前正在处理的一些未完成的未命中。 如果未完成的未命中的数量大于或等于阈值，则系统停止对高速缓冲存储器的后续访问的生成，直到高速缓冲存储器中的每个集合的未完成未命中的数量低于阈值。 响应未完成的错误从存储子系统接收到高速缓存行时，系统识别未完成的未命中的集合。 然后，系统将缓存行安装在与集合相关联的条目中。 该系统还减少了目前正在进行的一些未完成的未命中。 如果由于递减而导致未完成的错失次数低于阈值，并且如果没有其他集合具有大于或等于阈值的未完成未命中的数量，则系统移除失速条件，使得后续访问可以 为缓存生成。

公开(公告)号：US06453463B1

公开(公告)日：2002-09-17

申请号：US09327397

申请日：1999-06-07

申请人： Shailender Chaudhry ,  Marc Tremblay

发明人： Shailender Chaudhry ,  Marc Tremblay

IPC分类号： G06F9446

CPC分类号： G06F9/3851 ,  G06F9/3842 ,  G06F9/3861

摘要： One embodiment of the present invention provides a system that facilitates marking of objects defined within an object-oriented programming system to keep track of accesses to fields within the objects. The system operates by receiving a reference to a field within an object, and identifying a marking bit within the object that is associated with the field. Note that each marking bit within the object is associated with a different subset of fields within the object. Next, the system sets the marking bit to indicate that at least one field within the associated subset of fields has been referenced. Finally, the system performs the reference to the field. In one embodiment of the present invention, the object includes N marking bits numbered 0, 1, 2, . . . , N−1 and M fields numbered 0, 1, 2, . . . , M−1. In this embodiment, the system identifies the marking bit associated with the field by starting with a field number for the field, and applying a modulo N operation to the field number to produce a number for the associated marking bit. In a variation on this embodiment, N is a power of two.

摘要翻译： 本发明的一个实施例提供了一种有助于在面向对象的编程系统内定义的对象的标记的系统，以便跟踪对对象内的字段的访问。 该系统通过接收对对象内的字段的引用来操作，以及识别该对象内与该字段相关联的标记位。 请注意，对象内的每个标记位都与对象中不同的字段子集相关联。 接下来，系统设置标记位以指示相关联的子集中的至少一个字段已经被引用。 最后，系统执行对该字段的引用。 在本发明的一个实施例中，对象包括编号为0,1,2的N个标记位。 。 。 ，N-1和M个字段编号为0,1,2。 。 。 ，M-1。 在该实施例中，系统通过从场的字段号开始，识别与该字段相关联的标记位，以及向场号应用模N运算以产生相关标记位的数字。 在该实施例的变型中，N是2的幂。

公开(公告)号：US06415356B1

公开(公告)日：2002-07-02

申请号：US09565637

申请日：2000-05-04

申请人： Shailender Chaudhry ,  Marc Tremblay

发明人： Shailender Chaudhry ,  Marc Tremblay

IPC分类号： G06F938

CPC分类号： G06F9/3877 ,  G06F9/3842

摘要： One embodiment of the present invention provides a system that prefetches from memory by using an assist processor that executes in advance of a primary processor. The system operates by executing executable code on the primary processor, and simultaneously executing a reduced version of the executable code on the assist processor. This reduced version runs more quickly than the executable code, and generates the same pattern of memory references as the executable code. This allows the assist processor to generate the same pattern of memory references that the primary processor generates in advance of when the primary processor generates the memory references. The system stores results of memory references generated by the assist processor in a store that is shared with the primary processor so that the primary processor can access the results of the memory references. In one embodiment of the present invention, this store is a cache memory. In one embodiment of the present invention, prior to executing the executable code, the system compiles source code into the executable code for the primary processor. The system also produces the reduced version of the executable code for the assist processor from the executable code by eliminating instructions from the executable code that have no effect on a pattern of memory references generated by the executable code.

摘要翻译： 本发明的一个实施例提供一种通过使用在主处理器之前执行的辅助处理器来从存储器预取的系统。 该系统通过在主处理器上执行可执行代码来操作，并且在辅助处理器上同时执行可执行代码的简化版本。 这个简化版本比可执行代码运行得更快，并且生成与可执行代码相同的内存引用模式。 这允许辅助处理器在主处理器产生存储器引用之前产生与主处理器产生的相同的存储器引用模式。 系统将由辅助处理器生成的存储器引用的结果存储在与主处理器共享的存储器中，使得主处理器可以访问存储器引用的结果。 在本发明的一个实施例中，该存储器是高速缓存存储器。 在本发明的一个实施例中，在执行可执行代码之前，系统将源代码编译成主处理器的可执行代码。 该系统还通过从可执行代码中消除对由可执行代码生成的存储器引用的模式没有影响的指令，从可执行代码产生辅助处理器的可执行代码的简化版本。

公开(公告)号：US06247027B1

公开(公告)日：2001-06-12

申请号：US09313243

申请日：1999-05-17

申请人： Shailender Chaudhry ,  Marc Tremblay

发明人： Shailender Chaudhry ,  Marc Tremblay

IPC分类号： G06F1730

CPC分类号： G06F12/0253 ,  G06F12/0269 ,  Y10S707/99953 ,  Y10S707/99957

摘要： One embodiment of the present invention provides a system that facilitates garbage collection and supports space and time dimensional execution of a computer program. The system executes program instructions with a head thread and speculatively executes program instructions in advance of the head thread with a speculative thread. During execution of the speculative thread, the system creates space-time dimensioned versions of objects from a system heap that are modified by the speculative thread. These space-time dimensioned versions of objects are created in a speculative heap that is separate from the system heap. The system keeps a record of objects for which space-time dimensioned versions have been created during updates to value fields and during updates to pointer fields by the speculative thread. This record is used during a garbage collection operation to identify live objects so that the garbage collection operation can move the live objects from the speculative heap to the system heap. In one embodiment of the present invention, if the speculative thread causes a hazard condition, the system performs a rollback. This rollback uses the record to identify objects in the system heap that have been modified by the speculative thread so that the modifications can be undone. Note that a hazard condition can occur if the head thread writes to a field that was read by the speculative thread, or alternatively if the head thread writes to a space-time dimensioned version of an object that was written to by the speculative thread.

摘要翻译： 本发明的一个实施例提供一种便于垃圾收集并支持计算机程序的空间和时间尺寸执行的系统。 该系统使用头部线程执行程序指令，并用推测性线程在头部线程之前推测性地执行程序指令。 在推测线程的执行过程中，系统从系统堆中创建由推测线程修改的对象的时空维度版本。 这些空间时间的对象版本是在与系统堆分开的推测堆中创建的。 系统保留在更新期间创建空间时间尺寸版本的对象的记录，并在推测线程更新指针字段期间。 在垃圾收集操作期间使用该记录来识别活动对象，以便垃圾回收操作可以将活动对象从推测堆移动到系统堆。 在本发明的一个实施例中，如果推测线引起危险状况，则系统执行回滚。 此回滚使用记录来标识系统堆中已被推测性线程修改的对象，以便可以撤销修改。 请注意，如果头线程写入由推测线程读取的字段，或者头部线程写入由推测线程写入的对象的时空尺寸版本，则可能会发生危险状况。

公开(公告)号：US07836290B2

公开(公告)日：2010-11-16

申请号：US11363625

申请日：2006-02-28

申请人： Shailender Chaudhry ,  Quinn A. Jacobson ,  Paul Caprioli ,  Marc Tremblay

发明人： Shailender Chaudhry ,  Quinn A. Jacobson ,  Paul Caprioli ,  Marc Tremblay

IPC分类号： G06F9/44

CPC分类号： G06F9/3806 ,  G06F9/3863 ,  G06F9/3867

摘要： A technique recovers return address stack (RAS) content and restores alignment of a RAS top-of-stack (TOS) pointer for occurrences of mispredictions due to speculative operation, out-of-order instruction processing, and exception handling. In at least one embodiment of the invention, an apparatus includes a speculative execution processor pipeline, a first structure for maintaining return addresses relative to instruction flow at a first stage of the pipeline, at least a second structure for maintaining return addresses relative to instruction flow at a second stage of the pipeline. The second stage of the pipeline is deeper in the pipeline than the first stage. The apparatus includes circuitry operable to reproduce at least return addresses from the second structure to the first structure.

摘要翻译： 一种技术恢复返回地址堆栈（RAS）内容，并恢复RAS堆栈顶部（TOS）指针的对齐，用于由于推测操作，无序指令处理和异常处理引起的错误预测。 在本发明的至少一个实施例中，一种装置包括推测执行处理器流水线，用于在流水线的第一阶段保持相对于指令流的返回地址的第一结构，用于维持相对于指令流的返回地址的至少第二结构 在管道的第二阶段。 管道的第二阶段比第一阶段管道更深。 该装置包括可操作以至少将从第二结构返回地址再现到第一结构的电路。

公开(公告)号：US07836281B1

公开(公告)日：2010-11-16

申请号：US11245774

申请日：2005-10-06

申请人： Marc Tremblay ,  Shailender Chaudhry

发明人： Marc Tremblay ,  Shailender Chaudhry

IPC分类号： G06F9/30 ,  G06F9/40 ,  G06F7/38 ,  G06F9/00 ,  G06F9/44

CPC分类号： G06F9/3836 ,  G06F9/30105 ,  G06F9/3838 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/3859 ,  G06F9/3863 ,  G06F9/3865

摘要： A system that facilitates improving performance of a processor during scout mode. During a normal-execution mode, the system executes instructions for using main thread. Upon encountering a stall condition during execution of the main thread, the system generates a checkpoint. The system then enters a scout mode, wherein instructions are speculatively executed by a speculative thread to prefetch future memory references, but results are not committed to the architectural state of the processor. Upon encountering a memory reference during scout mode, the system issues a prefetch for the memory reference. If the stall condition that caused the processor to enter scout mode is resolved, the system uses the checkpoint to resume execution of the main thread from the instruction that caused the stall condition, and simultaneously continues executing instructions in scout mode using the speculative thread from the point where the speculative thread left off.

摘要翻译： 一种有助于在侦察模式下提高处理器性能的系统。 在正常执行模式下，系统执行使用主线程的指令。 在主线程执行过程中遇到停顿状态时，系统生成检查点。 然后，系统进入侦察模式，其中由推测性线程推测地执行指令以预取将来的存储器引用，但是结果未被提交到处理器的架构状态。 在侦察模式期间遇到存储器引用时，系统发出存储器引用的预取。 如果解决了导致处理器进入侦察模式的停顿条件，系统将使用检查点从导致失速状态的指令中恢复主线程的执行，并同时继续执行侦察模式中的指令，使用来自 点投机线暂停。

公开(公告)号：US07689813B2

公开(公告)日：2010-03-30

申请号：US11083263

申请日：2005-03-16

申请人： Paul Caprioli ,  Shailender Chaudhry ,  Marc Tremblay

发明人： Paul Caprioli ,  Shailender Chaudhry ,  Marc Tremblay

IPC分类号： G06F9/30 ,  G06F9/40

CPC分类号： G06F9/30087 ,  G06F9/3004 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3842 ,  G06F9/3857

摘要： Embodiments of the present invention provide a system that facilitates executing a memory barrier (membar) instruction in an execute-ahead processor, wherein the membar instruction forces buffered loads and stores to complete before allowing a following instruction to be issued.

摘要翻译： 本发明的实施例提供了一种便于在执行前处理器中执行存储器屏障（membar）指令的系统，其中，在允许执行后续指令之前，该指令强制缓冲的负载和存储完成。

公开(公告)号：US07519775B2

公开(公告)日：2009-04-14

申请号：US11592835

申请日：2006-11-03

申请人： Shailender Chaudhry ,  Marc Tremblay

发明人： Shailender Chaudhry ,  Marc Tremblay

IPC分类号： G06F12/00

CPC分类号： G06F12/0897

摘要： One embodiment of the present invention provides a system that enforces memory-reference ordering requirements at an L2 cache. During operation, the system receives a load at the L2 cache, wherein the load previously caused a miss at an L1cache. Upon receiving the load, the system performs a lookup for the load in reflections of store buffers associated with other L1 caches. These reflections are located at the L2 cache, and each reflection contains addresses for stores in a corresponding store buffer associated with an L1 cache, and possibly contains data that was overwritten by the stores. If the lookup generates a hit, which indicates that the load may potentially interfere with a store, the system causes the load to wait to execute until the store commits.

摘要翻译： 本发明的一个实施例提供一种在L2高速缓存上实施存储器参考排序要求的系统。 在运行期间，系统在L2高速缓存中接收到一个负载，其中负载先前在L1cache处引起了一个缺失。 在接收到负载后，系统以与其他L1高速缓存相关联的存储缓冲器的反射来执行对负载的查找。 这些反射位于L2高速缓存中，每个反射都包含与L1缓存相关联的存储缓冲器中的存储地址，并且可能包含由存储器覆盖的数据。 如果查找生成一个命中，这表明该负载可能潜在地干扰一个存储，系统会导致负载等待执行，直到存储提交。

公开(公告)号：US07366880B2

公开(公告)日：2008-04-29

申请号：US11340076

申请日：2006-01-25

申请人： Shailender Chaudhry ,  Marc Tremblay

发明人： Shailender Chaudhry ,  Marc Tremblay

IPC分类号： G06F9/30

CPC分类号： G06F9/3842 ,  G06F9/383 ,  G06F9/3851

摘要： One embodiment of the present invention provides a system that predicts a result produced by a section of code in order to support speculative program execution. The system begins by executing the section of code using a head thread in order to produce a result. Before the head thread produces the result, the system generates a predicted result to be used in place of the result. Next, the system allows a speculative thread to use the predicted result in speculatively executing subsequent code that follows the section of code. After the head thread finishes executing the section of code, the system determines if a difference between the predicted result and the result generated by the head thread has affected execution of the speculative thread. If so, the system executes the subsequent code again using the result generated by the head thread. If not, the system performs a join operation to merge state associated with the speculative thread with state associated with the head thread. In one embodiment of the present invention, executing the subsequent code again involves performing a rollback operation for the speculative thread to undo actions performed by the speculative thread.

摘要翻译： 本发明的一个实施例提供了一种系统，其预测由代码段产生的结果，以便支持推测程序的执行。 系统通过使用头部线程执行代码段来开始，以产生结果。 在头线程产生结果之前，系统生成要用于取代结果的预测结果。 接下来，系统允许推测线程使用预测结果来推测地执行跟随代码段的后续代码。 在头线程完成执行代码段之后，系统确定预测结果与头线程生成的结果之间的差异是否影响了推测线程的执行。 如果是这样，系统将使用头线程生成的结果再次执行后续代码。 如果不是，则系统执行连接操作以将与推测线程相关联的状态与与头部线程相关联的状态合并。 在本发明的一个实施例中，再次执行后续代码涉及对推测线程执行回滚操作来撤销推测线程执行的动作。