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    Fin Structure and Method of Forming Same Through Two-Step Etching Processes
    91.
    发明申请
    Fin Structure and Method of Forming Same Through Two-Step Etching Processes 有权

    公开(公告)号：US20210066290A1

    公开(公告)日：2021-03-04

    申请号：US17097423

    申请日：2020-11-13

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

    IPC: H01L27/088 ,  H01L27/12 ,  H01L21/84 ,  H01L29/08 ,  H01L21/8234

    Abstract: A method includes, in a first etching step, etching a semiconductor substrate to form first recesses in a first device region and second recesses in a second device regions simultaneously. A first semiconductor strip is formed between the first recesses. A second semiconductor strip is formed between the second recesses. In a second etching step, the semiconductor substrate in the second device region is etched to extend the second recesses. The first recesses and the second recesses are filled with a dielectric material to form first and second isolation regions in the first and second recesses, respectively. The first isolation regions and the second isolation regions are recessed. Portions of the semiconductor substrate in the first and the second device regions protrude higher than top surfaces of the respective first and second isolation regions to form a first and a second semiconductor fin, respectively.

    Fin-type field effect transistor structure and manufacturing method thereof
    94.
    发明授权
    Fin-type field effect transistor structure and manufacturing method thereof 有权

    公开(公告)号：US10727227B2

    公开(公告)日：2020-07-28

    申请号：US16447973

    申请日：2019-06-21

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Che-Cheng Chang ,  Chih-Han Lin

    IPC: H01L27/08 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/49

    Abstract: A fin-type field effect transistor comprising a substrate, at least one gate structure, spacers and source and drain regions is described. The substrate has a plurality of fins and a plurality of insulators disposed between the fins. The source and drain regions are disposed on two opposite sides of the at least one gate structure. The gate structure is disposed over the plurality of fins and disposed on the plurality of insulators. The gate structure includes a stacked strip disposed on the substrate and a gate electrode stack disposed on the stacked strip. The spacers are disposed on opposite sidewalls of the gate structure, and the gate electrode stack contacts sidewalls of the opposite spacers.

    Semiconductor device and manufacturing method thereof
    95.
    发明授权
    Semiconductor device and manufacturing method thereof 有权

    公开(公告)号：US10658485B2

    公开(公告)日：2020-05-19

    申请号：US16383542

    申请日：2019-04-12

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Chih-Han Lin ,  Shih-Chang Tsai ,  Wen-Shuo Hsieh ,  Te-Yung Liu

    IPC: H01L29/78 ,  H01L29/49 ,  H01L29/786 ,  H01L27/04 ,  H01L21/8238 ,  H01L21/02 ,  H01L51/52 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/088 ,  H01L27/12

    Abstract: A semiconductor device includes plurality of fin structures extending in first direction on semiconductor substrate. Fin structure's lower portion is embedded in first insulating layer. First gate electrode and second gate electrode structures extend in second direction substantially perpendicular to first direction over of fin structures and first insulating layer. The first and second gate electrode structures are spaced apart and extend along line in same direction. First and second insulating sidewall spacers are arranged on opposing sides of first and second gate electrode structures. Each of first and second insulating sidewall spacers contiguously extend along second direction. A second insulating layer is in region between first and second gate electrode structures. The second insulating layer separates first and second gate electrode structures. A third insulating layer is in region between first and second gate electrode structures. The third insulating layer is formed of different material than second insulating layer.

    Methods of Forming Isolation Features in Metal Gates
    96.
    发明申请
    Methods of Forming Isolation Features in Metal Gates 审中-公开

    公开(公告)号：US20200098646A1

    公开(公告)日：2020-03-26

    申请号：US16452101

    申请日：2019-06-25

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chang-Yin Chen ,  Che-Cheng Chang ,  Chih-Han Lin

    IPC: H01L21/8238 ,  H01L21/8234

    Abstract: A method for fabricating a semiconductor device includes providing a structure having two fins over a substrate, lower portions of the fins being separated by an isolation structure, a dummy gate structure over the fins, and source/drain features over the fins on both sides of the dummy gate structure; forming a trench in the dummy gate structure between the two fins, where forming the trench removes a portion of the isolation structure; forming a dielectric layer in the trench, where a bottom surface of the dielectric layer extends below a top surface of the isolation structure; and replacing the dummy gate structure with one high-k metal gate structure formed over one of the fins and another high-k metal gate structure formed over the other of the fins.

    Method for manufacturing semiconductor device
    100.
    发明授权
    Method for manufacturing semiconductor device 有权

    公开(公告)号：US10510896B2

    公开(公告)日：2019-12-17

    申请号：US16041664

    申请日：2018-07-20

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Che-Cheng Chang ,  Chih-Han Lin

    IPC: H01L21/00 ,  H01L29/78 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66

    Abstract: A method includes forming an insulating structure over a substrate, wherein the substrate has a semiconductor fin separated from the insulating structure; depositing a high-κ dielectric layer over the semiconductor fin and a sidewall of the insulating structure facing the semiconductor fin; etching a first portion of the high-κ dielectric layer over the sidewall of the insulating structure, wherein a second portion of the high-κ dielectric layer remains over the semiconductor fin; and depositing a gate electrode over the second portion of the high-κ dielectric layer.

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