公开(公告)号：US20150026444A1

公开(公告)日：2015-01-22

申请号：US14334352

申请日：2014-07-17

Applicant: Texas Instruments Incorporated

Inventor： Timothy D. Anderson ,  Joseph Zbiciak ,  Duc Q. Bui ,  Mel A. Phipps ,  Todd T. Hahn

IPC: G06F9/30 ,  G06F9/48

CPC classification number: G06F9/4881 ,  G06F8/30 ,  G06F8/443 ,  G06F8/4442 ,  G06F9/3802 ,  G06F9/3834 ,  G06F9/3842

Abstract: A statically scheduled processor compiler schedules a speculative load in the program before the data is needed. The compiler inserts a conditional instruction confirming or disaffirming the speculative load before the program behavior changes due to the speculative load. The condition is not based solely upon whether the speculative load address is correct but preferably includes dependence according to the original source code. The compiler may statically schedule two or more branches in parallel with orthogonal conditions.

Abstract translation: 在需要数据之前，静态调度处理器编译器会在程序中调度一个推测性负载。 在程序行为由于推测负载而变化之前，编译器会插入一条条件指令来确认或不肯定推测负载。 该条件不仅仅基于推测负载地址是否正确，而且还包括根据原始源代码的依赖性。 编译器可以与正交条件并行地静态安排两个或更多个分支。

公开(公告)号：US20140149690A1

公开(公告)日：2014-05-29

申请号：US14061979

申请日：2013-10-24

Applicant: Texas Instruments Incorporated

Inventor： Kai Chirca ,  Matthew D. Pierson ,  Daniel B. Wu ,  Timothy D. Anderson

IPC: G06F12/08 ,  G06F13/42

CPC classification number: G06F21/78 ,  G06F12/0815 ,  G06F12/0828 ,  G06F12/0831 ,  G06F12/0835 ,  G06F12/0842 ,  G06F12/1081 ,  G06F12/1458 ,  G06F12/1491 ,  G06F13/1626 ,  G06F13/1663 ,  G06F13/287 ,  G06F13/4022 ,  G06F13/42 ,  G06F21/79 ,  G06F2212/1032 ,  G06F2212/283 ,  G06F2212/62 ,  G06F2212/621 ,  H04L63/0263 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: This invention combines a multicore shared memory controller and an asynchronous protocol converting bridge to create a very efficient heterogeneous multi-processor system. After traversing the protocol converting bridge the commands travel through the regular processor port. This allows the interconnect to remain unchanged while having any combination of different processors connected. This invention tightly integrates all of the processors into the same memory controller/interconnect.

Abstract translation: 本发明结合了多核共享存储器控制器和异步协议转换桥以创建非常有效的异构多处理器系统。 在通过协议转换网桥之后，命令行进通过常规处理器端口。 这允许互连保持不变，同时连接不同处理器的任何组合。 本发明将所有处理器紧密地集成到相同的存储器控​​制器/互连中。

公开(公告)号：US20140115271A1

公开(公告)日：2014-04-24

申请号：US14057205

申请日：2013-10-18

Applicant: Texas Instruments Incorporated

Inventor： Matthew D. Pierson ,  Kai Chirca ,  Timothy D. Anderson

IPC: G06F12/08

CPC classification number: G06F21/78 ,  G06F12/0815 ,  G06F12/0828 ,  G06F12/0831 ,  G06F12/0835 ,  G06F12/0842 ,  G06F12/1081 ,  G06F12/1458 ,  G06F12/1491 ,  G06F13/1626 ,  G06F13/1663 ,  G06F13/287 ,  G06F13/4022 ,  G06F13/42 ,  G06F21/79 ,  G06F2212/1032 ,  G06F2212/283 ,  G06F2212/62 ,  G06F2212/621 ,  H04L63/0263 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: This invention speeds operation for coherence writes to shared memory. This invention immediately commits to the memory endpoint coherence write data. Thus this data will be available earlier than if the memory controller stalled this write pending snoop responses. This invention computes write enable strobes for the coherence write data based upon the cache dirty tags. This invention initiates a snoop cycle based upon the address of the coherence write. The stored write enable strobes enable determination of which data to write to the endpoint memory upon a cached and dirty snoop response.

Abstract translation: 本发明加速了对共享存储器的一致性写操作。 本发明立即提交到存储器端点一致写入数据。 因此，如果内存控制器停止了这个写入挂起的侦听响应，那么这个数据将可用。 本发明基于高速缓存脏标签计算用于相干写入数据的写入使能选通。 本发明基于一致性写入的地址启动窥探循环。 存储的写使能选通使得能够确定在高速缓存和脏的窥探响应时哪些数据写入端点存储器。