公开(公告)号：US20080288753A1

公开(公告)日：2008-11-20

申请号：US12183086

申请日：2008-07-31

申请人： Brian Michael Stempel ,  James Norris Dieffenderfer ,  Thomas Andrew Sartorius ,  Rodney Wayne Smith

发明人： Brian Michael Stempel ,  James Norris Dieffenderfer ,  Thomas Andrew Sartorius ,  Rodney Wayne Smith

IPC分类号： G06F9/30

CPC分类号： G06F9/3844 ,  G06F9/3005 ,  G06F9/30058 ,  G06F9/30101 ,  G06F9/322 ,  G06F9/3806

摘要： An apparatus for emulating the branch prediction behavior of an explicit subroutine call is disclosed. The apparatus includes a first input which is configured to receive an instruction address and a second input. The second input is configured to receive predecode information which describes the instruction address as being related to an implicit subroutine call to a subroutine. In response to the predecode information, the apparatus also includes an adder configured to add a constant to the instruction address defining a return address, causing the return address to be stored to an explicit subroutine resource, thus, facilitating subsequent branch prediction of a return call instruction.

公开(公告)号：US20080250229A1

公开(公告)日：2008-10-09

申请号：US11696508

申请日：2007-04-04

申请人： Brian Michael Stempel ,  Thomas Andrew Sartorius ,  Rodney Wayne Smith

发明人： Brian Michael Stempel ,  Thomas Andrew Sartorius ,  Rodney Wayne Smith

IPC分类号： G06F9/30

CPC分类号： G06F9/30047 ,  G06F9/30152 ,  G06F9/3802 ,  G06F9/382

摘要： In a processor executing instructions from a variable-length instruction set, a preload instruction is operative to retrieve from memory a data block corresponding to an instruction cache line, pre-decode instructions from a variable-length instruction set in the data block, and load the instructions and pre-decode information into the instruction cache. An instruction execution unit indicates to a pre-decoder the position within the data block of a first valid instruction. The pre-decoder successively determines the length of each instruction and hence the instruction boundaries. An instruction cache line offset indicator that identifies the position of the first valid instruction may be generated and provided to the pre-decoder in a variety of ways.

摘要翻译： 在执行来自可变长度指令集的指令的处理器中，预加载指令用于从存储器检索与指令高速缓存行相对应的数据块，对来自数据块中的可变长度指令集的指令进行预解码，以及负载 指令和预解码信息到指令缓存中。 指令执行单元向预解码器指示第一有效指令的数据块内的位置。 预解码器依次确定每个指令的长度，从而确定指令边界。 可以以各种方式生成识别第一有效指令的位置的指令高速缓存行偏移指示符并将其提供给预解码器。

公开(公告)号：US20080177987A1

公开(公告)日：2008-07-24

申请号：US11626424

申请日：2007-01-24

申请人： Michael Scott McIlvaine ,  James Norris Dieffenderfer ,  Nathan Samuel Nunamaker ,  Thomas Andrew Sartorius ,  Rodney Wayne Smith

发明人： Michael Scott McIlvaine ,  James Norris Dieffenderfer ,  Nathan Samuel Nunamaker ,  Thomas Andrew Sartorius ,  Rodney Wayne Smith

IPC分类号： G06F9/312

CPC分类号： G06F9/3017 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857

摘要： Intermediate results are passed between constituent instructions of an expanded instruction using register renaming resources and control logic. A first constituent instruction generates intermediate results and is assigned a PRN in a constituent instruction rename table, and writes intermediate results to the identified physical register. A second constituent instruction performs a look up in the constituent instruction rename table and reads the intermediate results from the physical register. Constituent instruction rename logic tracks the constituent instructions through the pipeline, and delete the constituent instruction rename table entry and returns the PRN to a free list when the second constituent instruction has read the intermediate results.

摘要翻译： 使用寄存器重命名资源和控制逻辑在扩展指令的组成指令之间传递中间结果。 第一组成指令生成中间结果，并在组成指令重命名表中分配PRN，并将中间结果写入所识别的物理寄存器。 第二个构成指令在组成指令重命名表中执行查询，并从物理寄存器读取中间结果。 组分指令重命名逻辑通过流水线跟踪组成指令，并删除组成指令重命名表项，并在第二组成指令读取中间结果时将PRN返回到空闲列表。

公开(公告)号：US20080040587A1

公开(公告)日：2008-02-14

申请号：US11463379

申请日：2006-08-09

申请人： Kevin Charles Burke ,  Brian Michael Stempel ,  Daren Streett ,  Kevin Allen Sapp ,  Leslie Mark DeBruyne ,  Nabil Amir Rizk ,  Thomas Andrew Sartorius ,  Rodney Wayne Smith

发明人： Kevin Charles Burke ,  Brian Michael Stempel ,  Daren Streett ,  Kevin Allen Sapp ,  Leslie Mark DeBruyne ,  Nabil Amir Rizk ,  Thomas Andrew Sartorius ,  Rodney Wayne Smith

IPC分类号： G06F9/44

CPC分类号： G06F11/3648

摘要： A processor is operative to execute two or more instruction sets, each in a different instruction set operating mode. As each instruction is executed, debug circuit comparison the current instruction set operating mode to a target instruction set operating mode sent by a programmer, and outputs an alert or indication in they match. The alert or indication may additionally be dependent upon the instruction address following within a predetermined target address range. The alert or indication may comprise a breakpoint signal that halts execution and/or it is output as an external signal of the processor. The instruction address at which the processor detects a match in the instruction set operating modes may additionally be output. Additionally or alternatively, the alert or indication may comprise starting or stopping a trace operation, causing an exception, or any other known debugger function.

摘要翻译： 处理器可操作以执行两个或更多个指令集，每个指令集处于不同的指令集操作模式。 当执行每条指令时，调试电路将当前指令集操作模式与编程器发送的目标指令集操作模式进行比较，并输出其中的警报或指示。 警报或指示还可以依赖于在预定目标地址范围内的指令地址。 警报或指示可以包括停止执行的断点信号和/或作为处理器的外部信号输出的断点信号。 可以另外输出处理器在指令集操作模式中检测到匹配的指令地址。 附加地或替代地，警报或指示可以包括启动或停止跟踪操作，引起异常或任何其他已知的调试器功能。

公开(公告)号：US20080034187A1

公开(公告)日：2008-02-07

申请号：US11461883

申请日：2006-08-02

申请人： Brian Michael Stempel ,  Thomas Andrew Sartorius ,  Rodney Wayne Smith

发明人： Brian Michael Stempel ,  Thomas Andrew Sartorius ,  Rodney Wayne Smith

IPC分类号： G06F12/00

CPC分类号： G06F9/3804 ,  G06F9/3806

摘要： A processor performs a prefetch operation on non-sequential instruction addresses. If a first instruction address misses in an instruction cache and accesses a higher-order memory as part of a fetch operation, and a branch instruction associated with the first instruction address or an address following the first instruction address is detected and predicted taken, a prefetch operation is performed using a predicted branch target address, during the higher-order memory access. If the predicted branch target address hits in the instruction cache during the prefetch operation, associated instructions are not retrieved, to conserve power. If the predicted branch target address misses in the instruction cache during the prefetch operation, a higher-order memory access may be launched, using the predicted branch instruction address. In either case, the first instruction address is re-loaded into the fetch stage pipeline to await the return of instructions from its higher-order memory access.

摘要翻译： 处理器对非顺序指令地址执行预取操作。 如果第一指令地址在指令高速缓存中丢失并且作为获取操作的一部分访问高阶存储器，并且检测并预测与第一指令地址或第一指令地址之后的地址相关联的分支指令，则预取 在高级存储器访问期间使用预测的分支目标地址执行操作。 如果预取分支目标地址在预取操作期间在指令高速缓存中命中，则不检索相关联的指令以节省功率。 如果在预取操作期间预测的分支目标地址在指令高速缓存中丢失，则可以使用预测的分支指令地址来启动高阶存储器访问。 在任一种情况下，第一指令地址被重新加载到提取级流水线中以等待指令从其高阶存储器访问返回。

公开(公告)号：US09092358B2

公开(公告)日：2015-07-28

申请号：US13371506

申请日：2012-02-13

申请人： Bohuslav Rychlik ,  Thomas Andrew Sartorius ,  Michael William Morrow ,  Raymond P. Palma

发明人： Bohuslav Rychlik ,  Thomas Andrew Sartorius ,  Michael William Morrow ,  Raymond P. Palma

IPC分类号： G06F13/00 ,  G06F13/28 ,  G06F12/10

CPC分类号： G06F12/1027 ,  G06F2212/6026 ,  G06F2212/6028 ,  G06F2212/654

摘要： Systems and method for memory management units (MMUs) configured to automatically pre-fill a translation lookaside buffer (TLB) with address translation entries expected to be used in the future, thereby reducing TLB miss rate and improving performance. The TLB may be pre-filled with translation entries, wherein addresses corresponding to the pre-fill may be selected based on predictions. Predictions may be derived from external devices, or based on stride values, wherein the stride values may be a predetermined constant or dynamically altered based on access patterns. Pre-filling the TLB may effectively remove latency involved in determining address translations for TLB misses from the critical path.

摘要翻译： 用于内存管理单元（MMU）的系统和方法被配置为自动预先填充具有将要使用的地址转换条目的翻译后备缓冲器（TLB），从而减少TLB未命中率并提高性能。 可以预先填充TLB，其中可以基于预测来选择与预填充相对应的地址。 预测可以从外部设备导出，或者基于步幅值，其中步幅值可以是预定常数或基于访问模式动态地改变。 预填充TLB可以有效地消除从关键路径确定TLB未命中的地址转换所涉及的延迟。

公开(公告)号：US08938602B2

公开(公告)日：2015-01-20

申请号：US13565434

申请日：2012-08-02

申请人： Colin Christopher Sharp ,  Thomas Andrew Sartorius

发明人： Colin Christopher Sharp ,  Thomas Andrew Sartorius

IPC分类号： G06F12/00 ,  G06F13/00

CPC分类号： G06F12/1009 ,  G06F12/145 ,  G06F2212/656 ,  Y02D10/13

摘要： A first processing unit and a second processing unit can access a system memory that stores a common page table that is common to the first processing unit and the second processing unit. The common page table can store virtual memory addresses to physical memory addresses mapping for memory chunks accessed by a job of an application. A page entry, within the common page table, can include a first set of attribute bits that defines accessibility of the memory chunk by the first processing unit, a second set of attribute bits that defines accessibility of the same memory chunk by the second processing unit, and physical address bits that define a physical address of the memory chunk.

摘要翻译： 第一处理单元和第二处理单元可以访问存储第一处理单元和第二处理单元共用的公共页表的系统存储器。 公共页表可以将虚拟内存地址存储到由应用程序的作业访问的存储块的物理内存地址映射。 公共页表内的页条目可以包括第一组属性位，其定义第一处理单元对存储块的可访问性;第二组属性位，其定义第二处理单元的相同存储块的可访问性 ，以及定义存储块的物理地址的物理地址位。

公开(公告)号：US08924685B2

公开(公告)日：2014-12-30

申请号：US12777324

申请日：2010-05-11

申请人： Thomas Andrew Sartorius

发明人： Thomas Andrew Sartorius

IPC分类号： G06F12/10 ,  G06F9/34 ,  G06F9/35

CPC分类号： G06F9/34 ,  G06F9/35 ,  G06F12/1027 ,  G06F12/1081 ,  Y02D10/13

摘要： Configuring a surrogate memory accessing agent using an instruction for translating and storing a data value is described. In one embodiment, the instruction is received that includes a first operand specifying a data value to be translated and a second operand specifying a virtual address associated with a location of a surrogate memory accessing agent register in which to store the data value. The data value can be translated to a first physical address. The virtual address can be translated to a second physical address. The first physical address is stored in the surrogate memory accessing agent register based on the second physical address.

摘要翻译： 描述使用用于翻译和存储数据值的指令来配置代理存储器访问代理。 在一个实施例中，接收包括指定要转换的数据值的第一操作数和指定与其中存储数据值的代理存储器访问代理寄存器的位置相关联的虚拟地址的第二操作数的指令。 数据值可以转换为第一个物理地址。 虚拟地址可以转换为第二个物理地址。 第一物理地址基于第二物理地址存储在代理存储器访问代理寄存器中。

公开(公告)号：US20140040593A1

公开(公告)日：2014-02-06

申请号：US13565434

申请日：2012-08-02

申请人： Colin Christopher Sharp ,  Thomas Andrew Sartorius

发明人： Colin Christopher Sharp ,  Thomas Andrew Sartorius

IPC分类号： G06F12/10

CPC分类号： G06F12/1009 ,  G06F12/145 ,  G06F2212/656 ,  Y02D10/13

摘要： A first processing unit and a second processing unit can access a system memory that stores a common page table that is common to the first processing unit and the second processing unit. The common page table can store virtual memory addresses to physical memory addresses mapping for memory chunks accessed by a job of an application. A page entry, within the common page table, can include a first set of attribute bits that defines accessibility of the memory chunk by the first processing unit, a second set of attribute bits that defines accessibility of the same memory chunk by the second processing unit, and physical address bits that define a physical address of the memory chunk.

摘要翻译： 第一处理单元和第二处理单元可以访问存储第一处理单元和第二处理单元共用的公共页表的系统存储器。 公共页表可以将虚拟内存地址存储到由应用程序的作业访问的存储块的物理内存地址映射。 公共页表内的页条目可以包括第一组属性位，其定义第一处理单元对存储块的可访问性;第二组属性位，其定义第二处理单元的相同存储块的可访问性 ，以及定义存储块的物理地址的物理地址位。

公开(公告)号：US20120226888A1

公开(公告)日：2012-09-06

申请号：US13371506

申请日：2012-02-13

申请人： Bohuslav Rychlik ,  Thomas Andrew Sartorius ,  Michael William Morrow ,  Raymond P. Palma

发明人： Bohuslav Rychlik ,  Thomas Andrew Sartorius ,  Michael William Morrow ,  Raymond P. Palma

IPC分类号： G06F12/10

CPC分类号： G06F12/1027 ,  G06F2212/6026 ,  G06F2212/6028 ,  G06F2212/654

摘要： Systems and method for memory management units (MMUs) configured to automatically pre-fill a translation lookaside buffer (TLB) with address translation entries expected to be used in the future, thereby reducing TLB miss rate and improving performance. The TLB may be pre-filled with translation entries, wherein addresses corresponding to the pre-fill may be selected based on predictions. Predictions may be derived from external devices, or based on stride values, wherein the stride values may be a predetermined constant or dynamically altered based on access patterns. Pre-filling the TLB may effectively remove latency involved in determining address translations for TLB misses from the critical path.

摘要翻译： 用于内存管理单元（MMU）的系统和方法被配置为自动预先填充具有将要使用的地址转换条目的翻译后备缓冲器（TLB），从而减少TLB未命中率并提高性能。 可以预先填充TLB，其中可以基于预测来选择与预填充相对应的地址。 预测可以从外部设备导出，或者基于步幅值，其中步幅值可以是预定常数，或者基于访问模式动态地改变。 预填充TLB可以有效地消除从关键路径确定TLB未命中的地址转换所涉及的延迟。